shader_recompiler: Add subpixel offset for correct rounding at `ImageGather`
On AMD a subpixel offset of 1/512 of the texel size is applied to the texture coordinates at a ImageGather call to ensure the rounding at the texel centers is done the same way as in Maxwell or other Nvidia architectures. See https://www.reedbeta.com/blog/texture-gathers-and-coordinate-precision/ for more details why this might be necessary. This should fix shadow artifacts at object edges in Zelda: Breath of the Wild (#9957, #6956).
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780240e697
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@ -143,6 +143,21 @@ IR::Inst* PrepareSparse(IR::Inst& inst) {
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}
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}
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return sparse_inst;
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return sparse_inst;
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}
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}
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std::string ImageGatherSubpixelOffset(const IR::TextureInstInfo& info, std::string_view texture,
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std::string_view coords) {
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switch (info.type) {
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case TextureType::Color2D:
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case TextureType::Color2DRect:
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return fmt::format("{}+vec2(0.001953125)/vec2(textureSize({}, 0))", coords, texture);
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case TextureType::ColorArray2D:
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case TextureType::ColorCube:
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return fmt::format("vec3({0}.xy+vec2(0.001953125)/vec2(textureSize({1}, 0)),{0}.z)", coords,
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texture);
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default:
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return std::string{coords};
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}
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}
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} // Anonymous namespace
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} // Anonymous namespace
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void EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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void EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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@ -340,6 +355,13 @@ void EmitImageGather(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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LOG_WARNING(Shader_GLSL, "Device does not support sparse texture queries. STUBBING");
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LOG_WARNING(Shader_GLSL, "Device does not support sparse texture queries. STUBBING");
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ctx.AddU1("{}=true;", *sparse_inst);
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ctx.AddU1("{}=true;", *sparse_inst);
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}
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}
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std::string coords_with_subpixel_offset;
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if (ctx.profile.need_gather_subpixel_offset) {
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// Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on
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// AMD hardware as on Maxwell or other Nvidia architectures.
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coords_with_subpixel_offset = ImageGatherSubpixelOffset(info, texture, coords);
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coords = coords_with_subpixel_offset;
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}
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if (!sparse_inst || !supports_sparse) {
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if (!sparse_inst || !supports_sparse) {
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if (offset.IsEmpty()) {
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if (offset.IsEmpty()) {
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ctx.Add("{}=textureGather({},{},int({}));", texel, texture, coords,
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ctx.Add("{}=textureGather({},{},int({}));", texel, texture, coords,
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@ -387,6 +409,13 @@ void EmitImageGatherDref(EmitContext& ctx, IR::Inst& inst, const IR::Value& inde
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LOG_WARNING(Shader_GLSL, "Device does not support sparse texture queries. STUBBING");
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LOG_WARNING(Shader_GLSL, "Device does not support sparse texture queries. STUBBING");
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ctx.AddU1("{}=true;", *sparse_inst);
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ctx.AddU1("{}=true;", *sparse_inst);
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}
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}
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std::string coords_with_subpixel_offset;
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if (ctx.profile.need_gather_subpixel_offset) {
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// Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on
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// AMD hardware as on Maxwell or other Nvidia architectures.
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coords_with_subpixel_offset = ImageGatherSubpixelOffset(info, texture, coords);
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coords = coords_with_subpixel_offset;
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}
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if (!sparse_inst || !supports_sparse) {
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if (!sparse_inst || !supports_sparse) {
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if (offset.IsEmpty()) {
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if (offset.IsEmpty()) {
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ctx.Add("{}=textureGather({},{},{});", texel, texture, coords, dref);
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ctx.Add("{}=textureGather({},{},{});", texel, texture, coords, dref);
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@ -261,6 +261,39 @@ Id BitTest(EmitContext& ctx, Id mask, Id bit) {
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const Id bit_value{ctx.OpBitwiseAnd(ctx.U32[1], shifted, ctx.Const(1u))};
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const Id bit_value{ctx.OpBitwiseAnd(ctx.U32[1], shifted, ctx.Const(1u))};
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return ctx.OpINotEqual(ctx.U1, bit_value, ctx.u32_zero_value);
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return ctx.OpINotEqual(ctx.U1, bit_value, ctx.u32_zero_value);
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}
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}
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Id ImageGatherSubpixelOffset(EmitContext& ctx, const IR::TextureInstInfo& info, Id texture,
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Id coords) {
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// Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on
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// AMD hardware as on Maxwell or other Nvidia architectures.
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const auto calculate_offset{[&](size_t dim) -> std::array<Id, 2> {
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const Id nudge{ctx.Const(0x1p-9f)};
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const Id image_size{ctx.OpImageQuerySizeLod(ctx.U32[dim], texture, ctx.u32_zero_value)};
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const Id offset_x{ctx.OpFDiv(
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ctx.F32[1], nudge,
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ctx.OpConvertUToF(ctx.F32[1], ctx.OpCompositeExtract(ctx.U32[1], image_size, 0)))};
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const Id offset_y{ctx.OpFDiv(
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ctx.F32[1], nudge,
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ctx.OpConvertUToF(ctx.F32[1], ctx.OpCompositeExtract(ctx.U32[1], image_size, 1)))};
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return {ctx.OpFAdd(ctx.F32[1], ctx.OpCompositeExtract(ctx.F32[1], coords, 0), offset_x),
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ctx.OpFAdd(ctx.F32[1], ctx.OpCompositeExtract(ctx.F32[1], coords, 1), offset_y)};
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}};
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switch (info.type) {
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case TextureType::Color2D:
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case TextureType::Color2DRect: {
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const auto offset{calculate_offset(2)};
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return ctx.OpCompositeConstruct(ctx.F32[2], offset[0], offset[1]);
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}
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case TextureType::ColorArray2D:
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case TextureType::ColorCube: {
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const auto offset{calculate_offset(3)};
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return ctx.OpCompositeConstruct(ctx.F32[3], offset[0], offset[1],
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ctx.OpCompositeExtract(ctx.F32[1], coords, 2));
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}
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default:
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return coords;
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}
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}
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} // Anonymous namespace
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} // Anonymous namespace
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Id EmitBindlessImageSampleImplicitLod(EmitContext&) {
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Id EmitBindlessImageSampleImplicitLod(EmitContext&) {
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@ -423,6 +456,9 @@ Id EmitImageGather(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id
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const IR::Value& offset, const IR::Value& offset2) {
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const IR::Value& offset, const IR::Value& offset2) {
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const auto info{inst->Flags<IR::TextureInstInfo>()};
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const auto info{inst->Flags<IR::TextureInstInfo>()};
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const ImageOperands operands(ctx, offset, offset2);
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const ImageOperands operands(ctx, offset, offset2);
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if (ctx.profile.need_gather_subpixel_offset) {
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coords = ImageGatherSubpixelOffset(ctx, info, TextureImage(ctx, info, index), coords);
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}
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return Emit(&EmitContext::OpImageSparseGather, &EmitContext::OpImageGather, ctx, inst,
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return Emit(&EmitContext::OpImageSparseGather, &EmitContext::OpImageGather, ctx, inst,
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ctx.F32[4], Texture(ctx, info, index), coords, ctx.Const(info.gather_component),
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ctx.F32[4], Texture(ctx, info, index), coords, ctx.Const(info.gather_component),
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operands.MaskOptional(), operands.Span());
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operands.MaskOptional(), operands.Span());
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@ -432,6 +468,9 @@ Id EmitImageGatherDref(EmitContext& ctx, IR::Inst* inst, const IR::Value& index,
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const IR::Value& offset, const IR::Value& offset2, Id dref) {
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const IR::Value& offset, const IR::Value& offset2, Id dref) {
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const auto info{inst->Flags<IR::TextureInstInfo>()};
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const auto info{inst->Flags<IR::TextureInstInfo>()};
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const ImageOperands operands(ctx, offset, offset2);
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const ImageOperands operands(ctx, offset, offset2);
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if (ctx.profile.need_gather_subpixel_offset) {
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coords = ImageGatherSubpixelOffset(ctx, info, TextureImage(ctx, info, index), coords);
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}
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return Emit(&EmitContext::OpImageSparseDrefGather, &EmitContext::OpImageDrefGather, ctx, inst,
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return Emit(&EmitContext::OpImageSparseDrefGather, &EmitContext::OpImageDrefGather, ctx, inst,
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ctx.F32[4], Texture(ctx, info, index), coords, dref, operands.MaskOptional(),
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ctx.F32[4], Texture(ctx, info, index), coords, dref, operands.MaskOptional(),
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operands.Span());
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operands.Span());
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@ -52,6 +52,10 @@ struct Profile {
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bool need_declared_frag_colors{};
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bool need_declared_frag_colors{};
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/// Prevents fast math optimizations that may cause inaccuracies
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/// Prevents fast math optimizations that may cause inaccuracies
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bool need_fastmath_off{};
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bool need_fastmath_off{};
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/// Some GPU vendors use a lower fixed point format of 16.8 when calculating pixel coordinates
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/// in the ImageGather instruction than the Maxwell architecture does. Applying an offset does
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/// fix this mismatching rounding behaviour.
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bool need_gather_subpixel_offset{};
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/// OpFClamp is broken and OpFMax + OpFMin should be used instead
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/// OpFClamp is broken and OpFMax + OpFMin should be used instead
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bool has_broken_spirv_clamp{};
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bool has_broken_spirv_clamp{};
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@ -169,6 +169,7 @@ Device::Device(Core::Frontend::EmuWindow& emu_window) {
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has_draw_texture = GLAD_GL_NV_draw_texture;
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has_draw_texture = GLAD_GL_NV_draw_texture;
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warp_size_potentially_larger_than_guest = !is_nvidia && !is_intel;
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warp_size_potentially_larger_than_guest = !is_nvidia && !is_intel;
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need_fastmath_off = is_nvidia;
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need_fastmath_off = is_nvidia;
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need_gather_subpixel_offset = is_amd;
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can_report_memory = GLAD_GL_NVX_gpu_memory_info;
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can_report_memory = GLAD_GL_NVX_gpu_memory_info;
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// At the moment of writing this, only Nvidia's driver optimizes BufferSubData on exclusive
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// At the moment of writing this, only Nvidia's driver optimizes BufferSubData on exclusive
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@ -160,6 +160,10 @@ public:
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return need_fastmath_off;
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return need_fastmath_off;
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}
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}
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bool NeedsGatherSubpixelOffset() const {
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return need_gather_subpixel_offset;
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}
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bool HasCbufFtouBug() const {
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bool HasCbufFtouBug() const {
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return has_cbuf_ftou_bug;
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return has_cbuf_ftou_bug;
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}
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}
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@ -225,6 +229,7 @@ private:
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bool has_draw_texture{};
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bool has_draw_texture{};
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bool warp_size_potentially_larger_than_guest{};
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bool warp_size_potentially_larger_than_guest{};
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bool need_fastmath_off{};
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bool need_fastmath_off{};
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bool need_gather_subpixel_offset{};
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bool has_cbuf_ftou_bug{};
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bool has_cbuf_ftou_bug{};
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bool has_bool_ref_bug{};
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bool has_bool_ref_bug{};
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bool can_report_memory{};
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bool can_report_memory{};
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@ -218,6 +218,7 @@ ShaderCache::ShaderCache(RasterizerOpenGL& rasterizer_, Core::Frontend::EmuWindo
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.lower_left_origin_mode = true,
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.lower_left_origin_mode = true,
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.need_declared_frag_colors = true,
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.need_declared_frag_colors = true,
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.need_fastmath_off = device.NeedsFastmathOff(),
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.need_fastmath_off = device.NeedsFastmathOff(),
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.need_gather_subpixel_offset = device.NeedsGatherSubpixelOffset(),
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.has_broken_spirv_clamp = true,
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.has_broken_spirv_clamp = true,
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.has_broken_unsigned_image_offsets = true,
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.has_broken_unsigned_image_offsets = true,
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@ -329,6 +329,7 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, const Device& device
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.lower_left_origin_mode = false,
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.lower_left_origin_mode = false,
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.need_declared_frag_colors = false,
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.need_declared_frag_colors = false,
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.need_gather_subpixel_offset = device.NeedsGatherSubpixelOffset(),
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.has_broken_spirv_clamp = driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS,
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.has_broken_spirv_clamp = driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS,
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.has_broken_spirv_position_input = driver_id == VK_DRIVER_ID_QUALCOMM_PROPRIETARY,
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.has_broken_spirv_position_input = driver_id == VK_DRIVER_ID_QUALCOMM_PROPRIETARY,
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@ -431,6 +431,7 @@ Device::Device(VkInstance instance_, vk::PhysicalDevice physical_, VkSurfaceKHR
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"AMD GCN4 and earlier have broken VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT");
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"AMD GCN4 and earlier have broken VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT");
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has_broken_cube_compatibility = true;
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has_broken_cube_compatibility = true;
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}
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}
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need_gather_subpixel_offset = true;
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}
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}
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if (extensions.sampler_filter_minmax && is_amd) {
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if (extensions.sampler_filter_minmax && is_amd) {
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// Disable ext_sampler_filter_minmax on AMD GCN4 and lower as it is broken.
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// Disable ext_sampler_filter_minmax on AMD GCN4 and lower as it is broken.
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@ -554,6 +554,10 @@ public:
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return features.robustness2.nullDescriptor;
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return features.robustness2.nullDescriptor;
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}
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}
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bool NeedsGatherSubpixelOffset() const {
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return need_gather_subpixel_offset;
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}
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u32 GetMaxVertexInputAttributes() const {
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u32 GetMaxVertexInputAttributes() const {
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return properties.properties.limits.maxVertexInputAttributes;
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return properties.properties.limits.maxVertexInputAttributes;
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}
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}
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@ -664,6 +668,7 @@ private:
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bool must_emulate_bgr565{}; ///< Emulates BGR565 by swizzling RGB565 format.
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bool must_emulate_bgr565{}; ///< Emulates BGR565 by swizzling RGB565 format.
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bool dynamic_state3_blending{}; ///< Has all blending features of dynamic_state3.
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bool dynamic_state3_blending{}; ///< Has all blending features of dynamic_state3.
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bool dynamic_state3_enables{}; ///< Has all enables features of dynamic_state3.
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bool dynamic_state3_enables{}; ///< Has all enables features of dynamic_state3.
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bool need_gather_subpixel_offset{}; ///< Needs offset at ImageGather for correct rounding.
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u64 device_access_memory{}; ///< Total size of device local memory in bytes.
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u64 device_access_memory{}; ///< Total size of device local memory in bytes.
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u32 sets_per_pool{}; ///< Sets per Description Pool
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u32 sets_per_pool{}; ///< Sets per Description Pool
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