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shader_recompiler: Add subpixel offset for correct rounding at `ImageGather`

On AMD a subpixel offset of 1/512 of the texel size is applied to the texture coordinates at a ImageGather call to ensure the rounding at the texel centers is done the same way as in Maxwell or other Nvidia architectures.
See https://www.reedbeta.com/blog/texture-gathers-and-coordinate-precision/ for more details why this might be necessary.

This should fix shadow artifacts at object edges in Zelda: Breath of the Wild (#9957, #6956).
This commit is contained in:
Wollnashorn 2023-04-05 01:29:46 +02:00
parent bbdfe1fab1
commit 780240e697
9 changed files with 86 additions and 0 deletions

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@ -143,6 +143,21 @@ IR::Inst* PrepareSparse(IR::Inst& inst) {
} }
return sparse_inst; return sparse_inst;
} }
std::string ImageGatherSubpixelOffset(const IR::TextureInstInfo& info, std::string_view texture,
std::string_view coords) {
switch (info.type) {
case TextureType::Color2D:
case TextureType::Color2DRect:
return fmt::format("{}+vec2(0.001953125)/vec2(textureSize({}, 0))", coords, texture);
case TextureType::ColorArray2D:
case TextureType::ColorCube:
return fmt::format("vec3({0}.xy+vec2(0.001953125)/vec2(textureSize({1}, 0)),{0}.z)", coords,
texture);
default:
return std::string{coords};
}
}
} // Anonymous namespace } // Anonymous namespace
void EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, void EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
@ -340,6 +355,13 @@ void EmitImageGather(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
LOG_WARNING(Shader_GLSL, "Device does not support sparse texture queries. STUBBING"); LOG_WARNING(Shader_GLSL, "Device does not support sparse texture queries. STUBBING");
ctx.AddU1("{}=true;", *sparse_inst); ctx.AddU1("{}=true;", *sparse_inst);
} }
std::string coords_with_subpixel_offset;
if (ctx.profile.need_gather_subpixel_offset) {
// Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on
// AMD hardware as on Maxwell or other Nvidia architectures.
coords_with_subpixel_offset = ImageGatherSubpixelOffset(info, texture, coords);
coords = coords_with_subpixel_offset;
}
if (!sparse_inst || !supports_sparse) { if (!sparse_inst || !supports_sparse) {
if (offset.IsEmpty()) { if (offset.IsEmpty()) {
ctx.Add("{}=textureGather({},{},int({}));", texel, texture, coords, ctx.Add("{}=textureGather({},{},int({}));", texel, texture, coords,
@ -387,6 +409,13 @@ void EmitImageGatherDref(EmitContext& ctx, IR::Inst& inst, const IR::Value& inde
LOG_WARNING(Shader_GLSL, "Device does not support sparse texture queries. STUBBING"); LOG_WARNING(Shader_GLSL, "Device does not support sparse texture queries. STUBBING");
ctx.AddU1("{}=true;", *sparse_inst); ctx.AddU1("{}=true;", *sparse_inst);
} }
std::string coords_with_subpixel_offset;
if (ctx.profile.need_gather_subpixel_offset) {
// Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on
// AMD hardware as on Maxwell or other Nvidia architectures.
coords_with_subpixel_offset = ImageGatherSubpixelOffset(info, texture, coords);
coords = coords_with_subpixel_offset;
}
if (!sparse_inst || !supports_sparse) { if (!sparse_inst || !supports_sparse) {
if (offset.IsEmpty()) { if (offset.IsEmpty()) {
ctx.Add("{}=textureGather({},{},{});", texel, texture, coords, dref); ctx.Add("{}=textureGather({},{},{});", texel, texture, coords, dref);

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@ -261,6 +261,39 @@ Id BitTest(EmitContext& ctx, Id mask, Id bit) {
const Id bit_value{ctx.OpBitwiseAnd(ctx.U32[1], shifted, ctx.Const(1u))}; const Id bit_value{ctx.OpBitwiseAnd(ctx.U32[1], shifted, ctx.Const(1u))};
return ctx.OpINotEqual(ctx.U1, bit_value, ctx.u32_zero_value); return ctx.OpINotEqual(ctx.U1, bit_value, ctx.u32_zero_value);
} }
Id ImageGatherSubpixelOffset(EmitContext& ctx, const IR::TextureInstInfo& info, Id texture,
Id coords) {
// Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on
// AMD hardware as on Maxwell or other Nvidia architectures.
const auto calculate_offset{[&](size_t dim) -> std::array<Id, 2> {
const Id nudge{ctx.Const(0x1p-9f)};
const Id image_size{ctx.OpImageQuerySizeLod(ctx.U32[dim], texture, ctx.u32_zero_value)};
const Id offset_x{ctx.OpFDiv(
ctx.F32[1], nudge,
ctx.OpConvertUToF(ctx.F32[1], ctx.OpCompositeExtract(ctx.U32[1], image_size, 0)))};
const Id offset_y{ctx.OpFDiv(
ctx.F32[1], nudge,
ctx.OpConvertUToF(ctx.F32[1], ctx.OpCompositeExtract(ctx.U32[1], image_size, 1)))};
return {ctx.OpFAdd(ctx.F32[1], ctx.OpCompositeExtract(ctx.F32[1], coords, 0), offset_x),
ctx.OpFAdd(ctx.F32[1], ctx.OpCompositeExtract(ctx.F32[1], coords, 1), offset_y)};
}};
switch (info.type) {
case TextureType::Color2D:
case TextureType::Color2DRect: {
const auto offset{calculate_offset(2)};
return ctx.OpCompositeConstruct(ctx.F32[2], offset[0], offset[1]);
}
case TextureType::ColorArray2D:
case TextureType::ColorCube: {
const auto offset{calculate_offset(3)};
return ctx.OpCompositeConstruct(ctx.F32[3], offset[0], offset[1],
ctx.OpCompositeExtract(ctx.F32[1], coords, 2));
}
default:
return coords;
}
}
} // Anonymous namespace } // Anonymous namespace
Id EmitBindlessImageSampleImplicitLod(EmitContext&) { Id EmitBindlessImageSampleImplicitLod(EmitContext&) {
@ -423,6 +456,9 @@ Id EmitImageGather(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id
const IR::Value& offset, const IR::Value& offset2) { const IR::Value& offset, const IR::Value& offset2) {
const auto info{inst->Flags<IR::TextureInstInfo>()}; const auto info{inst->Flags<IR::TextureInstInfo>()};
const ImageOperands operands(ctx, offset, offset2); const ImageOperands operands(ctx, offset, offset2);
if (ctx.profile.need_gather_subpixel_offset) {
coords = ImageGatherSubpixelOffset(ctx, info, TextureImage(ctx, info, index), coords);
}
return Emit(&EmitContext::OpImageSparseGather, &EmitContext::OpImageGather, ctx, inst, return Emit(&EmitContext::OpImageSparseGather, &EmitContext::OpImageGather, ctx, inst,
ctx.F32[4], Texture(ctx, info, index), coords, ctx.Const(info.gather_component), ctx.F32[4], Texture(ctx, info, index), coords, ctx.Const(info.gather_component),
operands.MaskOptional(), operands.Span()); operands.MaskOptional(), operands.Span());
@ -432,6 +468,9 @@ Id EmitImageGatherDref(EmitContext& ctx, IR::Inst* inst, const IR::Value& index,
const IR::Value& offset, const IR::Value& offset2, Id dref) { const IR::Value& offset, const IR::Value& offset2, Id dref) {
const auto info{inst->Flags<IR::TextureInstInfo>()}; const auto info{inst->Flags<IR::TextureInstInfo>()};
const ImageOperands operands(ctx, offset, offset2); const ImageOperands operands(ctx, offset, offset2);
if (ctx.profile.need_gather_subpixel_offset) {
coords = ImageGatherSubpixelOffset(ctx, info, TextureImage(ctx, info, index), coords);
}
return Emit(&EmitContext::OpImageSparseDrefGather, &EmitContext::OpImageDrefGather, ctx, inst, return Emit(&EmitContext::OpImageSparseDrefGather, &EmitContext::OpImageDrefGather, ctx, inst,
ctx.F32[4], Texture(ctx, info, index), coords, dref, operands.MaskOptional(), ctx.F32[4], Texture(ctx, info, index), coords, dref, operands.MaskOptional(),
operands.Span()); operands.Span());

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@ -52,6 +52,10 @@ struct Profile {
bool need_declared_frag_colors{}; bool need_declared_frag_colors{};
/// Prevents fast math optimizations that may cause inaccuracies /// Prevents fast math optimizations that may cause inaccuracies
bool need_fastmath_off{}; bool need_fastmath_off{};
/// Some GPU vendors use a lower fixed point format of 16.8 when calculating pixel coordinates
/// in the ImageGather instruction than the Maxwell architecture does. Applying an offset does
/// fix this mismatching rounding behaviour.
bool need_gather_subpixel_offset{};
/// OpFClamp is broken and OpFMax + OpFMin should be used instead /// OpFClamp is broken and OpFMax + OpFMin should be used instead
bool has_broken_spirv_clamp{}; bool has_broken_spirv_clamp{};

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@ -169,6 +169,7 @@ Device::Device(Core::Frontend::EmuWindow& emu_window) {
has_draw_texture = GLAD_GL_NV_draw_texture; has_draw_texture = GLAD_GL_NV_draw_texture;
warp_size_potentially_larger_than_guest = !is_nvidia && !is_intel; warp_size_potentially_larger_than_guest = !is_nvidia && !is_intel;
need_fastmath_off = is_nvidia; need_fastmath_off = is_nvidia;
need_gather_subpixel_offset = is_amd;
can_report_memory = GLAD_GL_NVX_gpu_memory_info; can_report_memory = GLAD_GL_NVX_gpu_memory_info;
// At the moment of writing this, only Nvidia's driver optimizes BufferSubData on exclusive // At the moment of writing this, only Nvidia's driver optimizes BufferSubData on exclusive

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@ -160,6 +160,10 @@ public:
return need_fastmath_off; return need_fastmath_off;
} }
bool NeedsGatherSubpixelOffset() const {
return need_gather_subpixel_offset;
}
bool HasCbufFtouBug() const { bool HasCbufFtouBug() const {
return has_cbuf_ftou_bug; return has_cbuf_ftou_bug;
} }
@ -225,6 +229,7 @@ private:
bool has_draw_texture{}; bool has_draw_texture{};
bool warp_size_potentially_larger_than_guest{}; bool warp_size_potentially_larger_than_guest{};
bool need_fastmath_off{}; bool need_fastmath_off{};
bool need_gather_subpixel_offset{};
bool has_cbuf_ftou_bug{}; bool has_cbuf_ftou_bug{};
bool has_bool_ref_bug{}; bool has_bool_ref_bug{};
bool can_report_memory{}; bool can_report_memory{};

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@ -218,6 +218,7 @@ ShaderCache::ShaderCache(RasterizerOpenGL& rasterizer_, Core::Frontend::EmuWindo
.lower_left_origin_mode = true, .lower_left_origin_mode = true,
.need_declared_frag_colors = true, .need_declared_frag_colors = true,
.need_fastmath_off = device.NeedsFastmathOff(), .need_fastmath_off = device.NeedsFastmathOff(),
.need_gather_subpixel_offset = device.NeedsGatherSubpixelOffset(),
.has_broken_spirv_clamp = true, .has_broken_spirv_clamp = true,
.has_broken_unsigned_image_offsets = true, .has_broken_unsigned_image_offsets = true,

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@ -329,6 +329,7 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, const Device& device
.lower_left_origin_mode = false, .lower_left_origin_mode = false,
.need_declared_frag_colors = false, .need_declared_frag_colors = false,
.need_gather_subpixel_offset = device.NeedsGatherSubpixelOffset(),
.has_broken_spirv_clamp = driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS, .has_broken_spirv_clamp = driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS,
.has_broken_spirv_position_input = driver_id == VK_DRIVER_ID_QUALCOMM_PROPRIETARY, .has_broken_spirv_position_input = driver_id == VK_DRIVER_ID_QUALCOMM_PROPRIETARY,

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@ -431,6 +431,7 @@ Device::Device(VkInstance instance_, vk::PhysicalDevice physical_, VkSurfaceKHR
"AMD GCN4 and earlier have broken VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT"); "AMD GCN4 and earlier have broken VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT");
has_broken_cube_compatibility = true; has_broken_cube_compatibility = true;
} }
need_gather_subpixel_offset = true;
} }
if (extensions.sampler_filter_minmax && is_amd) { if (extensions.sampler_filter_minmax && is_amd) {
// Disable ext_sampler_filter_minmax on AMD GCN4 and lower as it is broken. // Disable ext_sampler_filter_minmax on AMD GCN4 and lower as it is broken.

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@ -554,6 +554,10 @@ public:
return features.robustness2.nullDescriptor; return features.robustness2.nullDescriptor;
} }
bool NeedsGatherSubpixelOffset() const {
return need_gather_subpixel_offset;
}
u32 GetMaxVertexInputAttributes() const { u32 GetMaxVertexInputAttributes() const {
return properties.properties.limits.maxVertexInputAttributes; return properties.properties.limits.maxVertexInputAttributes;
} }
@ -664,6 +668,7 @@ private:
bool must_emulate_bgr565{}; ///< Emulates BGR565 by swizzling RGB565 format. bool must_emulate_bgr565{}; ///< Emulates BGR565 by swizzling RGB565 format.
bool dynamic_state3_blending{}; ///< Has all blending features of dynamic_state3. bool dynamic_state3_blending{}; ///< Has all blending features of dynamic_state3.
bool dynamic_state3_enables{}; ///< Has all enables features of dynamic_state3. bool dynamic_state3_enables{}; ///< Has all enables features of dynamic_state3.
bool need_gather_subpixel_offset{}; ///< Needs offset at ImageGather for correct rounding.
u64 device_access_memory{}; ///< Total size of device local memory in bytes. u64 device_access_memory{}; ///< Total size of device local memory in bytes.
u32 sets_per_pool{}; ///< Sets per Description Pool u32 sets_per_pool{}; ///< Sets per Description Pool