Merge pull request #9216 from vonchenplus/reimp_inline_index_buffer
video_core: Reimplement inline index buffer binding
This commit is contained in:
commit
7f1c6def1f
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@ -992,7 +992,20 @@ void BufferCache<P>::BindHostIndexBuffer() {
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TouchBuffer(buffer, index_buffer.buffer_id);
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TouchBuffer(buffer, index_buffer.buffer_id);
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const u32 offset = buffer.Offset(index_buffer.cpu_addr);
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const u32 offset = buffer.Offset(index_buffer.cpu_addr);
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const u32 size = index_buffer.size;
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const u32 size = index_buffer.size;
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SynchronizeBuffer(buffer, index_buffer.cpu_addr, size);
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if (maxwell3d->inline_index_draw_indexes.size()) {
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if constexpr (USE_MEMORY_MAPS) {
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auto upload_staging = runtime.UploadStagingBuffer(size);
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std::array<BufferCopy, 1> copies{
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{BufferCopy{.src_offset = upload_staging.offset, .dst_offset = 0, .size = size}}};
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std::memcpy(upload_staging.mapped_span.data(),
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maxwell3d->inline_index_draw_indexes.data(), size);
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runtime.CopyBuffer(buffer, upload_staging.buffer, copies);
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} else {
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buffer.ImmediateUpload(0, maxwell3d->inline_index_draw_indexes);
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}
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} else {
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SynchronizeBuffer(buffer, index_buffer.cpu_addr, size);
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}
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if constexpr (HAS_FULL_INDEX_AND_PRIMITIVE_SUPPORT) {
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if constexpr (HAS_FULL_INDEX_AND_PRIMITIVE_SUPPORT) {
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const u32 new_offset = offset + maxwell3d->regs.index_buffer.first *
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const u32 new_offset = offset + maxwell3d->regs.index_buffer.first *
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maxwell3d->regs.index_buffer.FormatSizeInBytes();
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maxwell3d->regs.index_buffer.FormatSizeInBytes();
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@ -1275,7 +1288,15 @@ void BufferCache<P>::UpdateIndexBuffer() {
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}
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}
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flags[Dirty::IndexBuffer] = false;
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flags[Dirty::IndexBuffer] = false;
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last_index_count = index_array.count;
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last_index_count = index_array.count;
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if (maxwell3d->inline_index_draw_indexes.size()) {
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auto inline_index_size = static_cast<u32>(maxwell3d->inline_index_draw_indexes.size());
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index_buffer = Binding{
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.cpu_addr = 0,
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.size = inline_index_size,
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.buffer_id = CreateBuffer(0, inline_index_size),
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};
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return;
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}
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const GPUVAddr gpu_addr_begin = index_array.StartAddress();
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const GPUVAddr gpu_addr_begin = index_array.StartAddress();
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const GPUVAddr gpu_addr_end = index_array.EndAddress();
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const GPUVAddr gpu_addr_end = index_array.EndAddress();
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const std::optional<VAddr> cpu_addr = gpu_memory->GpuToCpuAddress(gpu_addr_begin);
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const std::optional<VAddr> cpu_addr = gpu_memory->GpuToCpuAddress(gpu_addr_begin);
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@ -1491,6 +1512,14 @@ typename BufferCache<P>::OverlapResult BufferCache<P>::ResolveOverlaps(VAddr cpu
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VAddr end = cpu_addr + wanted_size;
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VAddr end = cpu_addr + wanted_size;
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int stream_score = 0;
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int stream_score = 0;
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bool has_stream_leap = false;
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bool has_stream_leap = false;
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if (begin == 0) {
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return OverlapResult{
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.ids = std::move(overlap_ids),
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.begin = begin,
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.end = end,
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.has_stream_leap = has_stream_leap,
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};
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}
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for (; cpu_addr >> YUZU_PAGEBITS < Common::DivCeil(end, YUZU_PAGESIZE);
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for (; cpu_addr >> YUZU_PAGEBITS < Common::DivCeil(end, YUZU_PAGESIZE);
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cpu_addr += YUZU_PAGESIZE) {
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cpu_addr += YUZU_PAGESIZE) {
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const BufferId overlap_id = page_table[cpu_addr >> YUZU_PAGEBITS];
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const BufferId overlap_id = page_table[cpu_addr >> YUZU_PAGEBITS];
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@ -222,8 +222,6 @@ void RasterizerOpenGL::Draw(bool is_indexed, u32 instance_count) {
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pipeline->SetEngine(maxwell3d, gpu_memory);
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pipeline->SetEngine(maxwell3d, gpu_memory);
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pipeline->Configure(is_indexed);
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pipeline->Configure(is_indexed);
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BindInlineIndexBuffer();
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SyncState();
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SyncState();
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const GLenum primitive_mode = MaxwellToGL::PrimitiveTopology(maxwell3d->regs.draw.topology);
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const GLenum primitive_mode = MaxwellToGL::PrimitiveTopology(maxwell3d->regs.draw.topology);
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@ -1140,16 +1138,6 @@ void RasterizerOpenGL::ReleaseChannel(s32 channel_id) {
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query_cache.EraseChannel(channel_id);
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query_cache.EraseChannel(channel_id);
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}
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}
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void RasterizerOpenGL::BindInlineIndexBuffer() {
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if (maxwell3d->inline_index_draw_indexes.empty()) {
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return;
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}
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const auto data_count = static_cast<u32>(maxwell3d->inline_index_draw_indexes.size());
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auto buffer = Buffer(buffer_cache_runtime, *this, 0, data_count);
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buffer.ImmediateUpload(0, maxwell3d->inline_index_draw_indexes);
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buffer_cache_runtime.BindIndexBuffer(buffer, 0, data_count);
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}
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AccelerateDMA::AccelerateDMA(BufferCache& buffer_cache_) : buffer_cache{buffer_cache_} {}
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AccelerateDMA::AccelerateDMA(BufferCache& buffer_cache_) : buffer_cache{buffer_cache_} {}
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bool AccelerateDMA::BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) {
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bool AccelerateDMA::BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) {
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@ -199,8 +199,6 @@ private:
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/// End a transform feedback
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/// End a transform feedback
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void EndTransformFeedback();
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void EndTransformFeedback();
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void BindInlineIndexBuffer();
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Tegra::GPU& gpu;
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Tegra::GPU& gpu;
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const Device& device;
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const Device& device;
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@ -191,8 +191,6 @@ void RasterizerVulkan::Draw(bool is_indexed, u32 instance_count) {
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pipeline->SetEngine(maxwell3d, gpu_memory);
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pipeline->SetEngine(maxwell3d, gpu_memory);
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pipeline->Configure(is_indexed);
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pipeline->Configure(is_indexed);
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BindInlineIndexBuffer();
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BeginTransformFeedback();
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BeginTransformFeedback();
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UpdateDynamicStates();
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UpdateDynamicStates();
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@ -1029,17 +1027,4 @@ void RasterizerVulkan::ReleaseChannel(s32 channel_id) {
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query_cache.EraseChannel(channel_id);
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query_cache.EraseChannel(channel_id);
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}
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}
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void RasterizerVulkan::BindInlineIndexBuffer() {
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if (maxwell3d->inline_index_draw_indexes.empty()) {
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return;
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}
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const auto data_count = static_cast<u32>(maxwell3d->inline_index_draw_indexes.size());
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auto buffer = buffer_cache_runtime.UploadStagingBuffer(data_count);
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std::memcpy(buffer.mapped_span.data(), maxwell3d->inline_index_draw_indexes.data(), data_count);
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buffer_cache_runtime.BindIndexBuffer(
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maxwell3d->regs.draw.topology, maxwell3d->regs.index_buffer.format,
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maxwell3d->regs.index_buffer.first, maxwell3d->regs.index_buffer.count, buffer.buffer,
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static_cast<u32>(buffer.offset), data_count);
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}
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} // namespace Vulkan
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} // namespace Vulkan
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@ -141,8 +141,6 @@ private:
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void UpdateVertexInput(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateVertexInput(Tegra::Engines::Maxwell3D::Regs& regs);
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void BindInlineIndexBuffer();
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Tegra::GPU& gpu;
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Tegra::GPU& gpu;
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ScreenInfo& screen_info;
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ScreenInfo& screen_info;
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