gl_shader_decompiler: Implement negate, abs, etc. and lots of cleanup.
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7639667562
commit
86135864da
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@ -56,15 +56,18 @@ union Attribute {
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Attribute_0 = 8,
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Attribute_0 = 8,
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};
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};
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constexpr Index GetIndex() const {
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union {
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return index;
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BitField<22, 2, u64> element;
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}
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BitField<24, 6, Index> index;
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BitField<47, 3, u64> size;
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} fmt20;
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union {
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BitField<30, 2, u64> element;
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BitField<32, 6, Index> index;
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} fmt28;
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public:
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BitField<24, 6, Index> index;
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BitField<22, 2, u64> element;
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BitField<39, 8, u64> reg;
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BitField<39, 8, u64> reg;
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BitField<47, 3, u64> size;
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u64 value;
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u64 value;
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};
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};
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@ -104,6 +107,7 @@ union OpCode {
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enum class Type {
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enum class Type {
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Trivial,
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Trivial,
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Arithmetic,
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Arithmetic,
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Ffma,
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Flow,
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Flow,
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Memory,
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Memory,
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Unknown,
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Unknown,
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@ -210,12 +214,11 @@ union OpCode {
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info_table[Id::TEXS] = {Type::Memory, "texs"};
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info_table[Id::TEXS] = {Type::Memory, "texs"};
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info_table[Id::LD_A] = {Type::Memory, "ld_a"};
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info_table[Id::LD_A] = {Type::Memory, "ld_a"};
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info_table[Id::ST_A] = {Type::Memory, "st_a"};
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info_table[Id::ST_A] = {Type::Memory, "st_a"};
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info_table[Id::IPA] = {Type::Arithmetic, "ipa"};
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info_table[Id::MUFU] = {Type::Arithmetic, "mufu"};
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info_table[Id::MUFU] = {Type::Arithmetic, "mufu"};
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info_table[Id::FFMA_IMM] = {Type::Arithmetic, "ffma_imm"};
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info_table[Id::FFMA_IMM] = {Type::Ffma, "ffma_imm"};
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info_table[Id::FFMA_CR] = {Type::Arithmetic, "ffma_cr"};
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info_table[Id::FFMA_CR] = {Type::Ffma, "ffma_cr"};
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info_table[Id::FFMA_RC] = {Type::Arithmetic, "ffma_rc"};
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info_table[Id::FFMA_RC] = {Type::Ffma, "ffma_rc"};
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info_table[Id::FFMA_RR] = {Type::Arithmetic, "ffma_rr"};
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info_table[Id::FFMA_RR] = {Type::Ffma, "ffma_rr"};
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info_table[Id::FADD_R] = {Type::Arithmetic, "fadd_r"};
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info_table[Id::FADD_R] = {Type::Arithmetic, "fadd_r"};
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info_table[Id::FADD_C] = {Type::Arithmetic, "fadd_c"};
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info_table[Id::FADD_C] = {Type::Arithmetic, "fadd_c"};
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info_table[Id::FADD_IMM] = {Type::Arithmetic, "fadd_imm"};
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info_table[Id::FADD_IMM] = {Type::Arithmetic, "fadd_imm"};
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@ -225,6 +228,7 @@ union OpCode {
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info_table[Id::FSETP_C] = {Type::Arithmetic, "fsetp_c"};
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info_table[Id::FSETP_C] = {Type::Arithmetic, "fsetp_c"};
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info_table[Id::FSETP_R] = {Type::Arithmetic, "fsetp_r"};
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info_table[Id::FSETP_R] = {Type::Arithmetic, "fsetp_r"};
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info_table[Id::EXIT] = {Type::Trivial, "exit"};
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info_table[Id::EXIT] = {Type::Trivial, "exit"};
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info_table[Id::IPA] = {Type::Trivial, "ipa"};
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info_table[Id::KIL] = {Type::Flow, "kil"};
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info_table[Id::KIL] = {Type::Flow, "kil"};
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return info_table;
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return info_table;
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}
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}
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@ -285,16 +289,31 @@ union Instruction {
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}
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}
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OpCode opcode;
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OpCode opcode;
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BitField<0, 8, Register> gpr1;
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BitField<0, 8, Register> gpr0;
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BitField<8, 8, Register> gpr2;
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BitField<8, 8, Register> gpr8;
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BitField<16, 4, Pred> pred;
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BitField<16, 4, Pred> pred;
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BitField<20, 8, Register> gpr20;
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BitField<20, 7, SubOp> sub_op;
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BitField<20, 7, SubOp> sub_op;
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BitField<39, 8, Register> gpr3;
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BitField<28, 8, Register> gpr28;
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BitField<45, 1, u64> nb;
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BitField<36, 13, u64> imm36;
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BitField<46, 1, u64> aa;
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BitField<39, 8, Register> gpr39;
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BitField<48, 1, u64> na;
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BitField<49, 1, u64> ab;
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union {
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BitField<50, 1, u64> ad;
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BitField<45, 1, u64> negate_b;
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BitField<46, 1, u64> abs_a;
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BitField<48, 1, u64> negate_a;
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BitField<49, 1, u64> abs_b;
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BitField<50, 1, u64> abs_d;
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} alu;
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union {
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BitField<48, 1, u64> negate_b;
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BitField<49, 1, u64> negate_c;
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} ffma;
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BitField<60, 1, u64> is_b_gpr;
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BitField<59, 1, u64> is_c_gpr;
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Attribute attribute;
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Attribute attribute;
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Uniform uniform;
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Uniform uniform;
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@ -17,6 +17,7 @@ using Tegra::Shader::Attribute;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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using Tegra::Shader::Register;
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using Tegra::Shader::SubOp;
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using Tegra::Shader::Uniform;
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using Tegra::Shader::Uniform;
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constexpr u32 PROGRAM_END = MAX_PROGRAM_CODE_LENGTH;
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constexpr u32 PROGRAM_END = MAX_PROGRAM_CODE_LENGTH;
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@ -235,27 +236,34 @@ private:
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switch (OpCode::GetInfo(instr.opcode).type) {
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switch (OpCode::GetInfo(instr.opcode).type) {
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case OpCode::Type::Arithmetic: {
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case OpCode::Type::Arithmetic: {
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ASSERT(!instr.nb);
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ASSERT(!instr.alu.abs_d, "unimplemented");
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ASSERT(!instr.aa);
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ASSERT(!instr.na);
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ASSERT(!instr.ab);
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ASSERT(!instr.ad);
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std::string gpr1 = GetRegister(instr.gpr1);
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std::string dest = GetRegister(instr.gpr0);
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std::string gpr2 = GetRegister(instr.gpr2);
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std::string op_a = instr.alu.negate_a ? "-" : "";
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std::string uniform = GetUniform(instr.uniform);
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op_a += GetRegister(instr.gpr8);
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if (instr.alu.abs_a) {
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op_a = "abs(" + op_a + ")";
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}
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std::string op_b = instr.alu.negate_b ? "-" : "";
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if (instr.is_b_gpr) {
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op_b += GetRegister(instr.gpr20);
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} else {
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op_b += GetUniform(instr.uniform);
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}
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if (instr.alu.abs_b) {
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op_b = "abs(" + op_b + ")";
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}
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switch (instr.opcode.EffectiveOpCode()) {
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switch (instr.opcode.EffectiveOpCode()) {
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case OpCode::Id::FMUL_C: {
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case OpCode::Id::FMUL_C:
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SetDest(0, gpr1, gpr2 + " * " + uniform, 1, 1);
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case OpCode::Id::FMUL_R: {
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SetDest(0, dest, op_a + " * " + op_b, 1, 1);
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break;
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break;
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}
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}
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case OpCode::Id::FADD_C: {
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case OpCode::Id::FADD_C:
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SetDest(0, gpr1, gpr2 + " + " + uniform, 1, 1);
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case OpCode::Id::FADD_R: {
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break;
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SetDest(0, dest, op_a + " + " + op_b, 1, 1);
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}
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case OpCode::Id::FFMA_CR: {
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SetDest(0, gpr1, gpr2 + " * " + uniform + " + " + GetRegister(instr.gpr3), 1, 1);
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break;
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break;
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}
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}
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default: {
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default: {
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@ -268,19 +276,48 @@ private:
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}
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}
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break;
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break;
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}
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}
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case OpCode::Type::Memory: {
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case OpCode::Type::Ffma: {
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ASSERT(instr.attribute.size == 0);
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ASSERT_MSG(!instr.ffma.negate_b, "untested");
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ASSERT_MSG(!instr.ffma.negate_c, "untested");
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std::string gpr1 = GetRegister(instr.gpr1);
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std::string dest = GetRegister(instr.gpr0);
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const Attribute::Index attribute = instr.attribute.GetIndex();
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std::string op_a = GetRegister(instr.gpr8);
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std::string op_b = instr.ffma.negate_b ? "-" : "";
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op_b += GetUniform(instr.uniform);
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std::string op_c = instr.ffma.negate_c ? "-" : "";
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op_c += GetRegister(instr.gpr39);
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switch (instr.opcode.EffectiveOpCode()) {
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case OpCode::Id::FFMA_CR: {
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SetDest(0, dest, op_a + " * " + op_b + " + " + op_c, 1, 1);
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break;
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}
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default: {
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LOG_ERROR(HW_GPU, "Unhandled arithmetic FFMA instruction: 0x%02x (%s): 0x%08x",
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(int)instr.opcode.EffectiveOpCode(), OpCode::GetInfo(instr.opcode).name,
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instr.hex);
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throw DecompileFail("Unhandled instruction");
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break;
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}
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}
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break;
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}
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case OpCode::Type::Memory: {
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std::string gpr0 = GetRegister(instr.gpr0);
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const Attribute::Index attribute = instr.attribute.fmt20.index;
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switch (instr.opcode.EffectiveOpCode()) {
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switch (instr.opcode.EffectiveOpCode()) {
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case OpCode::Id::LD_A: {
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case OpCode::Id::LD_A: {
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SetDest(instr.attribute.element, gpr1, GetInputAttribute(attribute), 1, 4);
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ASSERT(instr.attribute.fmt20.size == 0);
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SetDest(instr.attribute.fmt20.element, gpr0, GetInputAttribute(attribute), 1, 4);
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break;
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break;
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}
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}
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case OpCode::Id::ST_A: {
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case OpCode::Id::ST_A: {
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SetDest(instr.attribute.element, GetOutputAttribute(attribute), gpr1, 4, 1);
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ASSERT(instr.attribute.fmt20.size == 0);
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SetDest(instr.attribute.fmt20.element, GetOutputAttribute(attribute), gpr0, 4, 1);
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break;
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break;
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}
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}
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default: {
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default: {
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