dyncom: Remove more unused/unnecessary code
Gets rid of a sizeable amount of stuff in armdefs.
This commit is contained in:
parent
e3eba48596
commit
8b2b620a5e
|
@ -31,7 +31,6 @@ ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
|
|||
|
||||
// Reset the core to initial state
|
||||
ARMul_Reset(state.get());
|
||||
state->NextInstr = RESUME; // NOTE: This will be overwritten by LoadContext
|
||||
state->Emulate = RUN;
|
||||
|
||||
// Switch to the desired privilege mode.
|
||||
|
@ -99,7 +98,6 @@ void ARM_DynCom::ResetContext(Core::ThreadContext& context, u32 stack_top, u32 e
|
|||
context.pc = entry_point;
|
||||
context.sp = stack_top;
|
||||
context.cpsr = 0x1F; // Usermode
|
||||
context.mode = 8; // Instructs dyncom CPU core to start execution as if it's "resuming" a thread.
|
||||
}
|
||||
|
||||
void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) {
|
||||
|
@ -113,8 +111,6 @@ void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) {
|
|||
|
||||
ctx.fpscr = state->VFP[1];
|
||||
ctx.fpexc = state->VFP[2];
|
||||
|
||||
ctx.mode = state->NextInstr;
|
||||
}
|
||||
|
||||
void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) {
|
||||
|
@ -128,8 +124,6 @@ void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) {
|
|||
|
||||
state->VFP[1] = ctx.fpscr;
|
||||
state->VFP[2] = ctx.fpexc;
|
||||
|
||||
state->NextInstr = ctx.mode;
|
||||
}
|
||||
|
||||
void ARM_DynCom::PrepareReschedule() {
|
||||
|
|
|
@ -29,22 +29,8 @@ ARMul_State* ARMul_NewState(ARMul_State* state)
|
|||
memset(state, 0, sizeof(ARMul_State));
|
||||
|
||||
state->Emulate = RUN;
|
||||
for (unsigned int i = 0; i < 16; i++) {
|
||||
state->Reg[i] = 0;
|
||||
for (unsigned int j = 0; j < 7; j++)
|
||||
state->RegBank[j][i] = 0;
|
||||
}
|
||||
for (unsigned int i = 0; i < 7; i++)
|
||||
state->Spsr[i] = 0;
|
||||
|
||||
state->Mode = USER32MODE;
|
||||
|
||||
state->VectorCatch = 0;
|
||||
state->Aborted = false;
|
||||
state->Reseted = false;
|
||||
state->Inted = 3;
|
||||
state->LastInted = 3;
|
||||
|
||||
state->lateabtSig = HIGH;
|
||||
state->bigendSig = LOW;
|
||||
|
||||
|
@ -129,26 +115,18 @@ void ARMul_Reset(ARMul_State* state)
|
|||
{
|
||||
VFPInit(state);
|
||||
|
||||
state->NextInstr = 0;
|
||||
|
||||
state->Reg[15] = 0;
|
||||
state->Cpsr = INTBITS | SVC32MODE;
|
||||
state->Mode = SVC32MODE;
|
||||
|
||||
state->Bank = SVCBANK;
|
||||
FLUSHPIPE;
|
||||
|
||||
ResetMPCoreCP15Registers(state);
|
||||
|
||||
state->EndCondition = 0;
|
||||
state->ErrorCode = 0;
|
||||
|
||||
state->NresetSig = HIGH;
|
||||
state->NfiqSig = HIGH;
|
||||
state->NirqSig = HIGH;
|
||||
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
|
||||
state->abortSig = LOW;
|
||||
state->AbortAddr = 1;
|
||||
|
||||
state->NumInstrs = 0;
|
||||
}
|
||||
|
|
|
@ -53,14 +53,11 @@ typedef u64 ARMdword; // must be 64 bits wide
|
|||
typedef u32 ARMword; // must be 32 bits wide
|
||||
typedef u16 ARMhword; // must be 16 bits wide
|
||||
typedef u8 ARMbyte; // must be 8 bits wide
|
||||
typedef struct ARMul_State ARMul_State;
|
||||
|
||||
#define VFP_REG_NUM 64
|
||||
struct ARMul_State
|
||||
{
|
||||
ARMword Emulate; // To start and stop emulation
|
||||
unsigned EndCondition; // Reason for stopping
|
||||
unsigned ErrorCode; // Type of illegal instruction
|
||||
|
||||
// Order of the following register should not be modified
|
||||
ARMword Reg[16]; // The current register file
|
||||
|
@ -89,8 +86,6 @@ struct ARMul_State
|
|||
ARMword ExtReg[VFP_REG_NUM];
|
||||
/* ---- End of the ordered registers ---- */
|
||||
|
||||
ARMword RegBank[7][16]; // all the registers
|
||||
|
||||
ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed
|
||||
unsigned int shifter_carry_out;
|
||||
|
||||
|
@ -102,10 +97,7 @@ struct ARMul_State
|
|||
unsigned long long NumInstrs; // The number of instructions executed
|
||||
unsigned NumInstrsToExecute;
|
||||
|
||||
unsigned NextInstr;
|
||||
unsigned VectorCatch; // Caught exception mask
|
||||
|
||||
unsigned NresetSig; // Reset the processor
|
||||
unsigned NresetSig; // Reset the processor
|
||||
unsigned NfiqSig;
|
||||
unsigned NirqSig;
|
||||
|
||||
|
@ -147,13 +139,6 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
|
|||
*/
|
||||
unsigned lateabtSig;
|
||||
|
||||
bool Aborted; // Sticky flag for aborts
|
||||
bool Reseted; // Sticky flag for Reset
|
||||
ARMword Inted, LastInted; // Sticky flags for interrupts
|
||||
ARMword Base; // Extra hand for base writeback
|
||||
ARMword AbortAddr; // To keep track of Prefetch aborts
|
||||
ARMword Vector; // Synthesize aborts in cycle modes
|
||||
|
||||
// For differentiating ARM core emulaiton.
|
||||
bool is_v4; // Are we emulating a v4 architecture (or higher)?
|
||||
bool is_v5; // Are we emulating a v5 architecture?
|
||||
|
@ -167,14 +152,6 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
|
|||
|
||||
// Added by ksh in 2005-10-1
|
||||
cpu_config_t* cpu;
|
||||
|
||||
u32 CurrInstr;
|
||||
u32 last_pc; // The last PC executed
|
||||
u32 last_instr; // The last instruction executed
|
||||
u32 WriteAddr[17];
|
||||
u32 WriteData[17];
|
||||
u32 WritePc[17];
|
||||
u32 CurrWrite;
|
||||
};
|
||||
|
||||
/***************************************************************************\
|
||||
|
@ -260,34 +237,6 @@ enum {
|
|||
ARMul_INC = 3
|
||||
};
|
||||
|
||||
enum {
|
||||
ARMul_CP13_R0_FIQ = 0x1,
|
||||
ARMul_CP13_R0_IRQ = 0x2,
|
||||
ARMul_CP13_R8_PMUS = 0x1,
|
||||
|
||||
ARMul_CP14_R0_ENABLE = 0x0001,
|
||||
ARMul_CP14_R0_CLKRST = 0x0004,
|
||||
ARMul_CP14_R0_CCD = 0x0008,
|
||||
ARMul_CP14_R0_INTEN0 = 0x0010,
|
||||
ARMul_CP14_R0_INTEN1 = 0x0020,
|
||||
ARMul_CP14_R0_INTEN2 = 0x0040,
|
||||
ARMul_CP14_R0_FLAG0 = 0x0100,
|
||||
ARMul_CP14_R0_FLAG1 = 0x0200,
|
||||
ARMul_CP14_R0_FLAG2 = 0x0400,
|
||||
ARMul_CP14_R10_MOE_IB = 0x0004,
|
||||
ARMul_CP14_R10_MOE_DB = 0x0008,
|
||||
ARMul_CP14_R10_MOE_BT = 0x000c,
|
||||
ARMul_CP15_R1_ENDIAN = 0x0080,
|
||||
ARMul_CP15_R1_ALIGN = 0x0002,
|
||||
ARMul_CP15_R5_X = 0x0400,
|
||||
ARMul_CP15_R5_ST_ALIGN = 0x0001,
|
||||
ARMul_CP15_R5_IMPRE = 0x0406,
|
||||
ARMul_CP15_R5_MMU_EXCPT = 0x0400,
|
||||
ARMul_CP15_DBCON_M = 0x0100,
|
||||
ARMul_CP15_DBCON_E1 = 0x000c,
|
||||
ARMul_CP15_DBCON_E0 = 0x0003
|
||||
};
|
||||
|
||||
/***************************************************************************\
|
||||
* Definitons of things in the host environment *
|
||||
\***************************************************************************/
|
||||
|
|
|
@ -38,16 +38,6 @@ enum : u32 {
|
|||
INTBITS = 0x1C0,
|
||||
};
|
||||
|
||||
// Different ways to start the next instruction.
|
||||
enum {
|
||||
SEQ = 0,
|
||||
NONSEQ = 1,
|
||||
PCINCEDSEQ = 2,
|
||||
PCINCEDNONSEQ = 3,
|
||||
PRIMEPIPE = 4,
|
||||
RESUME = 8
|
||||
};
|
||||
|
||||
// Values for Emulate.
|
||||
enum {
|
||||
STOP = 0, // Stop
|
||||
|
@ -55,5 +45,3 @@ enum {
|
|||
ONCE = 2, // Execute just one interation
|
||||
RUN = 3 // Continuous execution
|
||||
};
|
||||
|
||||
#define FLUSHPIPE state->NextInstr |= PRIMEPIPE
|
||||
|
|
|
@ -21,9 +21,6 @@ struct ThreadContext {
|
|||
u32 fpu_registers[32];
|
||||
u32 fpscr;
|
||||
u32 fpexc;
|
||||
|
||||
// These are not part of native ThreadContext, but needed by emu
|
||||
u32 mode;
|
||||
};
|
||||
|
||||
extern ARM_Interface* g_app_core; ///< ARM11 application core
|
||||
|
|
Reference in New Issue