parent
2d422b2498
commit
8d470c2e63
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@ -70,6 +70,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/floating_point_compare.cpp
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frontend/maxwell/translate/impl/floating_point_compare.cpp
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frontend/maxwell/translate/impl/floating_point_conversion_integer.cpp
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frontend/maxwell/translate/impl/floating_point_conversion_integer.cpp
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frontend/maxwell/translate/impl/floating_point_fused_multiply_add.cpp
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frontend/maxwell/translate/impl/floating_point_fused_multiply_add.cpp
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frontend/maxwell/translate/impl/floating_point_min_max.cpp
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frontend/maxwell/translate/impl/floating_point_multi_function.cpp
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frontend/maxwell/translate/impl/floating_point_multi_function.cpp
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frontend/maxwell/translate/impl/floating_point_multiply.cpp
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frontend/maxwell/translate/impl/floating_point_multiply.cpp
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frontend/maxwell/translate/impl/floating_point_range_reduction.cpp
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frontend/maxwell/translate/impl/floating_point_range_reduction.cpp
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@ -162,10 +162,10 @@ Id EmitFPAdd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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Id EmitFPFma16(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
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Id EmitFPFma16(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
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Id EmitFPFma32(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
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Id EmitFPFma32(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
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Id EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
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Id EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
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void EmitFPMax32(EmitContext& ctx);
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Id EmitFPMax32(EmitContext& ctx, Id a, Id b);
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void EmitFPMax64(EmitContext& ctx);
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Id EmitFPMax64(EmitContext& ctx, Id a, Id b);
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void EmitFPMin32(EmitContext& ctx);
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Id EmitFPMin32(EmitContext& ctx, Id a, Id b);
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void EmitFPMin64(EmitContext& ctx);
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Id EmitFPMin64(EmitContext& ctx, Id a, Id b);
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Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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Id EmitFPMul32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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Id EmitFPMul32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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Id EmitFPMul64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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Id EmitFPMul64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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@ -60,20 +60,20 @@ Id EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) {
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return Decorate(ctx, inst, ctx.OpFma(ctx.F64[1], a, b, c));
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return Decorate(ctx, inst, ctx.OpFma(ctx.F64[1], a, b, c));
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}
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}
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void EmitFPMax32(EmitContext&) {
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Id EmitFPMax32(EmitContext& ctx, Id a, Id b) {
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throw NotImplementedException("SPIR-V Instruction");
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return ctx.OpFMax(ctx.F32[1], a, b);
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}
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}
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void EmitFPMax64(EmitContext&) {
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Id EmitFPMax64(EmitContext& ctx, Id a, Id b) {
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throw NotImplementedException("SPIR-V Instruction");
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return ctx.OpFMax(ctx.F64[1], a, b);
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}
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}
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void EmitFPMin32(EmitContext&) {
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Id EmitFPMin32(EmitContext& ctx, Id a, Id b) {
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throw NotImplementedException("SPIR-V Instruction");
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return ctx.OpFMin(ctx.F32[1], a, b);
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}
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}
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void EmitFPMin64(EmitContext&) {
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Id EmitFPMin64(EmitContext& ctx, Id a, Id b) {
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throw NotImplementedException("SPIR-V Instruction");
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return ctx.OpFMin(ctx.F64[1], a, b);
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}
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}
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Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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@ -831,6 +831,34 @@ U1 IREmitter::FPUnordered(const F32& lhs, const F32& rhs) {
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return LogicalOr(FPIsNan(lhs), FPIsNan(rhs));
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return LogicalOr(FPIsNan(lhs), FPIsNan(rhs));
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}
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}
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F32F64 IREmitter::FPMax(const F32F64& lhs, const F32F64& rhs, FpControl control) {
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if (lhs.Type() != rhs.Type()) {
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throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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}
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switch (lhs.Type()) {
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case Type::F32:
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return Inst<F32>(Opcode::FPMax32, Flags{control}, lhs, rhs);
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case Type::F64:
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return Inst<F64>(Opcode::FPMax64, Flags{control}, lhs, rhs);
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default:
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ThrowInvalidType(lhs.Type());
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}
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}
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F32F64 IREmitter::FPMin(const F32F64& lhs, const F32F64& rhs, FpControl control) {
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if (lhs.Type() != rhs.Type()) {
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throw InvalidArgument("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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}
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switch (lhs.Type()) {
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case Type::F32:
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return Inst<F32>(Opcode::FPMin32, Flags{control}, lhs, rhs);
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case Type::F64:
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return Inst<F64>(Opcode::FPMin64, Flags{control}, lhs, rhs);
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default:
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ThrowInvalidType(lhs.Type());
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}
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}
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U32U64 IREmitter::IAdd(const U32U64& a, const U32U64& b) {
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U32U64 IREmitter::IAdd(const U32U64& a, const U32U64& b) {
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if (a.Type() != b.Type()) {
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if (a.Type() != b.Type()) {
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throw InvalidArgument("Mismatching types {} and {}", a.Type(), b.Type());
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throw InvalidArgument("Mismatching types {} and {}", a.Type(), b.Type());
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@ -155,6 +155,8 @@ public:
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[[nodiscard]] U1 FPIsNan(const F32& value);
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[[nodiscard]] U1 FPIsNan(const F32& value);
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[[nodiscard]] U1 FPOrdered(const F32& lhs, const F32& rhs);
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[[nodiscard]] U1 FPOrdered(const F32& lhs, const F32& rhs);
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[[nodiscard]] U1 FPUnordered(const F32& lhs, const F32& rhs);
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[[nodiscard]] U1 FPUnordered(const F32& lhs, const F32& rhs);
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[[nodiscard]] F32F64 FPMax(const F32F64& lhs, const F32F64& rhs, FpControl control = {});
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[[nodiscard]] F32F64 FPMin(const F32F64& lhs, const F32F64& rhs, FpControl control = {});
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[[nodiscard]] U32U64 IAdd(const U32U64& a, const U32U64& b);
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[[nodiscard]] U32U64 IAdd(const U32U64& a, const U32U64& b);
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[[nodiscard]] U32U64 ISub(const U32U64& a, const U32U64& b);
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[[nodiscard]] U32U64 ISub(const U32U64& a, const U32U64& b);
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@ -88,7 +88,7 @@ void FCMP(TranslatorVisitor& v, u64 insn, const IR::U32& src_a, const IR::F32& o
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const IR::F32 zero{v.ir.Imm32(0.0f)};
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const IR::F32 zero{v.ir.Imm32(0.0f)};
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const IR::F32 neg_zero{v.ir.Imm32(-0.0f)};
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const IR::F32 neg_zero{v.ir.Imm32(-0.0f)};
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IR::FpControl control{.fmz_mode{fcmp.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None}};
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const IR::FpControl control{.fmz_mode{fcmp.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None}};
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const IR::U1 cmp_result{FloatingPointCompare(v.ir, operand, zero, fcmp.compare_op, control)};
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const IR::U1 cmp_result{FloatingPointCompare(v.ir, operand, zero, fcmp.compare_op, control)};
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const IR::U32 src_reg{v.X(fcmp.src_reg)};
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const IR::U32 src_reg{v.X(fcmp.src_reg)};
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const IR::U32 result{v.ir.Select(cmp_result, src_reg, src_a)};
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const IR::U32 result{v.ir.Select(cmp_result, src_reg, src_a)};
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@ -0,0 +1,57 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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void FMNMX(TranslatorVisitor& v, u64 insn, const IR::F32& src_b) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_a_reg;
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BitField<39, 3, IR::Pred> pred;
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BitField<42, 1, u64> neg_pred;
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BitField<44, 1, u64> ftz;
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BitField<45, 1, u64> negate_b;
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BitField<46, 1, u64> abs_a;
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BitField<48, 1, u64> negate_a;
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BitField<49, 1, u64> abs_b;
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} const fmnmx{insn};
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const IR::U1 pred{v.ir.GetPred(fmnmx.pred)};
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const IR::F32 op_a{v.ir.FPAbsNeg(v.F(fmnmx.src_a_reg), fmnmx.abs_a != 0, fmnmx.negate_a != 0)};
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const IR::F32 op_b = v.ir.FPAbsNeg(src_b, fmnmx.abs_b != 0, fmnmx.negate_b != 0);
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const IR::FpControl control{
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.no_contraction{false},
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.rounding{IR::FpRounding::DontCare},
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.fmz_mode{fmnmx.ftz != 0 ? IR::FmzMode::FTZ : IR::FmzMode::None},
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};
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IR::F32 max{v.ir.FPMax(op_a, op_b, control)};
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IR::F32 min{v.ir.FPMin(op_a, op_b, control)};
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if (fmnmx.neg_pred != 0) {
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std::swap(min, max);
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}
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v.F(fmnmx.dest_reg, IR::F32{v.ir.Select(pred, min, max)});
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}
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} // Anonymous namespace
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void TranslatorVisitor::FMNMX_reg(u64 insn) {
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FMNMX(*this, insn, GetFloatReg20(insn));
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}
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void TranslatorVisitor::FMNMX_cbuf(u64 insn) {
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FMNMX(*this, insn, GetFloatCbuf(insn));
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}
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void TranslatorVisitor::FMNMX_imm(u64 insn) {
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FMNMX(*this, insn, GetFloatImm20(insn));
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}
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} // namespace Shader::Maxwell
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@ -201,18 +201,6 @@ void TranslatorVisitor::FCHK_imm(u64) {
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ThrowNotImplemented(Opcode::FCHK_imm);
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ThrowNotImplemented(Opcode::FCHK_imm);
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}
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}
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void TranslatorVisitor::FMNMX_reg(u64) {
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ThrowNotImplemented(Opcode::FMNMX_reg);
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}
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void TranslatorVisitor::FMNMX_cbuf(u64) {
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ThrowNotImplemented(Opcode::FMNMX_cbuf);
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}
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void TranslatorVisitor::FMNMX_imm(u64) {
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ThrowNotImplemented(Opcode::FMNMX_imm);
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}
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void TranslatorVisitor::FSET_reg(u64) {
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void TranslatorVisitor::FSET_reg(u64) {
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ThrowNotImplemented(Opcode::FSET_reg);
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ThrowNotImplemented(Opcode::FSET_reg);
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}
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}
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Reference in New Issue