gl_rasterizer: Remove dirty flags
This commit is contained in:
ReinUsesLisp
parent
e38ed26b98
commit
96ac3d518a
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@ -69,6 +69,8 @@ add_library(video_core STATIC
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renderer_opengl/gl_shader_manager.h
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renderer_opengl/gl_shader_util.cpp
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renderer_opengl/gl_shader_util.h
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renderer_opengl/gl_state_tracker.cpp
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renderer_opengl/gl_state_tracker.h
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renderer_opengl/gl_state.cpp
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renderer_opengl/gl_state.h
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renderer_opengl/gl_stream_buffer.cpp
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@ -21,9 +21,6 @@ MICROPROFILE_DEFINE(DispatchCalls, "GPU", "Execute command buffer", MP_RGB(128,
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void DmaPusher::DispatchCalls() {
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MICROPROFILE_SCOPE(DispatchCalls);
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// On entering GPU code, assume all memory may be touched by the ARM core.
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gpu.Maxwell3D().dirty.OnMemoryWrite();
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dma_pushbuffer_subindex = 0;
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while (Core::System::GetInstance().IsPoweredOn()) {
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@ -38,9 +38,6 @@ void KeplerCompute::CallMethod(const GPU::MethodCall& method_call) {
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case KEPLER_COMPUTE_REG_INDEX(data_upload): {
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const bool is_last_call = method_call.IsLastCall();
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upload_state.ProcessData(method_call.argument, is_last_call);
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if (is_last_call) {
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system.GPU().Maxwell3D().dirty.OnMemoryWrite();
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}
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break;
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}
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case KEPLER_COMPUTE_REG_INDEX(launch):
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@ -33,9 +33,6 @@ void KeplerMemory::CallMethod(const GPU::MethodCall& method_call) {
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case KEPLERMEMORY_REG_INDEX(data): {
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const bool is_last_call = method_call.IsLastCall();
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upload_state.ProcessData(method_call.argument, is_last_call);
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if (is_last_call) {
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system.GPU().Maxwell3D().dirty.OnMemoryWrite();
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}
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break;
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}
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}
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@ -26,7 +26,6 @@ Maxwell3D::Maxwell3D(Core::System& system, VideoCore::RasterizerInterface& raste
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MemoryManager& memory_manager)
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: system{system}, rasterizer{rasterizer}, memory_manager{memory_manager},
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macro_interpreter{*this}, upload_state{memory_manager, regs.upload} {
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InitDirtySettings();
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InitializeRegisterDefaults();
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}
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@ -103,164 +102,6 @@ void Maxwell3D::InitializeRegisterDefaults() {
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mme_inline[MAXWELL3D_REG_INDEX(index_array.count)] = true;
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}
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#define DIRTY_REGS_POS(field_name) static_cast<u8>(offsetof(Maxwell3D::DirtyRegs, field_name))
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void Maxwell3D::InitDirtySettings() {
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const auto set_block = [this](std::size_t start, std::size_t range, u8 position) {
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const auto start_itr = dirty_pointers.begin() + start;
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const auto end_itr = start_itr + range;
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std::fill(start_itr, end_itr, position);
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};
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dirty.regs.fill(true);
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// Init Render Targets
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constexpr u32 registers_per_rt = sizeof(regs.rt[0]) / sizeof(u32);
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constexpr u32 rt_start_reg = MAXWELL3D_REG_INDEX(rt);
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constexpr u32 rt_end_reg = rt_start_reg + registers_per_rt * 8;
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u8 rt_dirty_reg = DIRTY_REGS_POS(render_target);
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for (u32 rt_reg = rt_start_reg; rt_reg < rt_end_reg; rt_reg += registers_per_rt) {
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set_block(rt_reg, registers_per_rt, rt_dirty_reg);
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++rt_dirty_reg;
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}
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constexpr u32 depth_buffer_flag = DIRTY_REGS_POS(depth_buffer);
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dirty_pointers[MAXWELL3D_REG_INDEX(zeta_enable)] = depth_buffer_flag;
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dirty_pointers[MAXWELL3D_REG_INDEX(zeta_width)] = depth_buffer_flag;
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dirty_pointers[MAXWELL3D_REG_INDEX(zeta_height)] = depth_buffer_flag;
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constexpr u32 registers_in_zeta = sizeof(regs.zeta) / sizeof(u32);
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constexpr u32 zeta_reg = MAXWELL3D_REG_INDEX(zeta);
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set_block(zeta_reg, registers_in_zeta, depth_buffer_flag);
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// Init Vertex Arrays
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constexpr u32 vertex_array_start = MAXWELL3D_REG_INDEX(vertex_array);
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constexpr u32 vertex_array_size = sizeof(regs.vertex_array[0]) / sizeof(u32);
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constexpr u32 vertex_array_end = vertex_array_start + vertex_array_size * Regs::NumVertexArrays;
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u8 va_dirty_reg = DIRTY_REGS_POS(vertex_array);
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u8 vi_dirty_reg = DIRTY_REGS_POS(vertex_instance);
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for (u32 vertex_reg = vertex_array_start; vertex_reg < vertex_array_end;
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vertex_reg += vertex_array_size) {
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set_block(vertex_reg, 3, va_dirty_reg);
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// The divisor concerns vertex array instances
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dirty_pointers[static_cast<std::size_t>(vertex_reg) + 3] = vi_dirty_reg;
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++va_dirty_reg;
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++vi_dirty_reg;
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}
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constexpr u32 vertex_limit_start = MAXWELL3D_REG_INDEX(vertex_array_limit);
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constexpr u32 vertex_limit_size = sizeof(regs.vertex_array_limit[0]) / sizeof(u32);
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constexpr u32 vertex_limit_end = vertex_limit_start + vertex_limit_size * Regs::NumVertexArrays;
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va_dirty_reg = DIRTY_REGS_POS(vertex_array);
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for (u32 vertex_reg = vertex_limit_start; vertex_reg < vertex_limit_end;
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vertex_reg += vertex_limit_size) {
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set_block(vertex_reg, vertex_limit_size, va_dirty_reg);
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va_dirty_reg++;
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}
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constexpr u32 vertex_instance_start = MAXWELL3D_REG_INDEX(instanced_arrays);
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constexpr u32 vertex_instance_size =
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sizeof(regs.instanced_arrays.is_instanced[0]) / sizeof(u32);
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constexpr u32 vertex_instance_end =
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vertex_instance_start + vertex_instance_size * Regs::NumVertexArrays;
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vi_dirty_reg = DIRTY_REGS_POS(vertex_instance);
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for (u32 vertex_reg = vertex_instance_start; vertex_reg < vertex_instance_end;
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vertex_reg += vertex_instance_size) {
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set_block(vertex_reg, vertex_instance_size, vi_dirty_reg);
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vi_dirty_reg++;
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}
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set_block(MAXWELL3D_REG_INDEX(vertex_attrib_format), regs.vertex_attrib_format.size(),
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DIRTY_REGS_POS(vertex_attrib_format));
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// Init Shaders
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constexpr u32 shader_registers_count =
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sizeof(regs.shader_config[0]) * Regs::MaxShaderProgram / sizeof(u32);
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set_block(MAXWELL3D_REG_INDEX(shader_config[0]), shader_registers_count,
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DIRTY_REGS_POS(shaders));
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// State
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// Viewport
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constexpr u8 viewport_dirty_reg = DIRTY_REGS_POS(viewport);
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constexpr u32 viewport_start = MAXWELL3D_REG_INDEX(viewports);
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constexpr u32 viewport_size = sizeof(regs.viewports) / sizeof(u32);
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set_block(viewport_start, viewport_size, viewport_dirty_reg);
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constexpr u32 view_volume_start = MAXWELL3D_REG_INDEX(view_volume_clip_control);
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constexpr u32 view_volume_size = sizeof(regs.view_volume_clip_control) / sizeof(u32);
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set_block(view_volume_start, view_volume_size, viewport_dirty_reg);
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// Viewport transformation
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constexpr u32 viewport_trans_start = MAXWELL3D_REG_INDEX(viewport_transform);
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constexpr u32 viewport_trans_size = sizeof(regs.viewport_transform) / sizeof(u32);
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set_block(viewport_trans_start, viewport_trans_size, DIRTY_REGS_POS(viewport_transform));
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// Cullmode
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constexpr u32 cull_mode_start = MAXWELL3D_REG_INDEX(cull);
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constexpr u32 cull_mode_size = sizeof(regs.cull) / sizeof(u32);
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set_block(cull_mode_start, cull_mode_size, DIRTY_REGS_POS(cull_mode));
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// Screen y control
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dirty_pointers[MAXWELL3D_REG_INDEX(screen_y_control)] = DIRTY_REGS_POS(screen_y_control);
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// Primitive Restart
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constexpr u32 primitive_restart_start = MAXWELL3D_REG_INDEX(primitive_restart);
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constexpr u32 primitive_restart_size = sizeof(regs.primitive_restart) / sizeof(u32);
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set_block(primitive_restart_start, primitive_restart_size, DIRTY_REGS_POS(primitive_restart));
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// Depth Test
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constexpr u8 depth_test_dirty_reg = DIRTY_REGS_POS(depth_test);
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dirty_pointers[MAXWELL3D_REG_INDEX(depth_test_enable)] = depth_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(depth_write_enabled)] = depth_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(depth_test_func)] = depth_test_dirty_reg;
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// Stencil Test
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constexpr u32 stencil_test_dirty_reg = DIRTY_REGS_POS(stencil_test);
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_enable)] = stencil_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_front_func_func)] = stencil_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_front_func_ref)] = stencil_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_front_func_mask)] = stencil_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_front_op_fail)] = stencil_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_front_op_zfail)] = stencil_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_front_op_zpass)] = stencil_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_front_mask)] = stencil_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_two_side_enable)] = stencil_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_back_func_func)] = stencil_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_back_func_ref)] = stencil_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_back_func_mask)] = stencil_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_back_op_fail)] = stencil_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_back_op_zfail)] = stencil_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_back_op_zpass)] = stencil_test_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_back_mask)] = stencil_test_dirty_reg;
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// Color Mask
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constexpr u8 color_mask_dirty_reg = DIRTY_REGS_POS(color_mask);
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dirty_pointers[MAXWELL3D_REG_INDEX(color_mask_common)] = color_mask_dirty_reg;
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set_block(MAXWELL3D_REG_INDEX(color_mask), sizeof(regs.color_mask) / sizeof(u32),
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color_mask_dirty_reg);
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// Blend State
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constexpr u8 blend_state_dirty_reg = DIRTY_REGS_POS(blend_state);
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set_block(MAXWELL3D_REG_INDEX(blend_color), sizeof(regs.blend_color) / sizeof(u32),
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blend_state_dirty_reg);
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dirty_pointers[MAXWELL3D_REG_INDEX(independent_blend_enable)] = blend_state_dirty_reg;
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set_block(MAXWELL3D_REG_INDEX(blend), sizeof(regs.blend) / sizeof(u32), blend_state_dirty_reg);
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set_block(MAXWELL3D_REG_INDEX(independent_blend), sizeof(regs.independent_blend) / sizeof(u32),
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blend_state_dirty_reg);
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// Scissor State
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constexpr u8 scissor_test_dirty_reg = DIRTY_REGS_POS(scissor_test);
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set_block(MAXWELL3D_REG_INDEX(scissor_test), sizeof(regs.scissor_test) / sizeof(u32),
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scissor_test_dirty_reg);
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// Polygon Offset
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constexpr u8 polygon_offset_dirty_reg = DIRTY_REGS_POS(polygon_offset);
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dirty_pointers[MAXWELL3D_REG_INDEX(polygon_offset_fill_enable)] = polygon_offset_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(polygon_offset_line_enable)] = polygon_offset_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(polygon_offset_point_enable)] = polygon_offset_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(polygon_offset_units)] = polygon_offset_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(polygon_offset_factor)] = polygon_offset_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(polygon_offset_clamp)] = polygon_offset_dirty_reg;
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// Depth bounds
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constexpr u8 depth_bounds_values_dirty_reg = DIRTY_REGS_POS(depth_bounds_values);
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dirty_pointers[MAXWELL3D_REG_INDEX(depth_bounds[0])] = depth_bounds_values_dirty_reg;
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dirty_pointers[MAXWELL3D_REG_INDEX(depth_bounds[1])] = depth_bounds_values_dirty_reg;
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}
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void Maxwell3D::CallMacroMethod(u32 method, std::size_t num_parameters, const u32* parameters) {
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// Reset the current macro.
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executing_macro = 0;
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@ -317,23 +158,7 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid Maxwell3D register, increase the size of the Regs structure");
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if (regs.reg_array[method] != method_call.argument) {
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regs.reg_array[method] = method_call.argument;
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const std::size_t dirty_reg = dirty_pointers[method];
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if (dirty_reg) {
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dirty.regs[dirty_reg] = true;
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if (dirty_reg >= DIRTY_REGS_POS(vertex_array) &&
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dirty_reg < DIRTY_REGS_POS(vertex_array_buffers)) {
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dirty.vertex_array_buffers = true;
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} else if (dirty_reg >= DIRTY_REGS_POS(vertex_instance) &&
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dirty_reg < DIRTY_REGS_POS(vertex_instances)) {
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dirty.vertex_instances = true;
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} else if (dirty_reg >= DIRTY_REGS_POS(render_target) &&
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dirty_reg < DIRTY_REGS_POS(render_settings)) {
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dirty.render_settings = true;
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}
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}
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}
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switch (method) {
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case MAXWELL3D_REG_INDEX(macros.data): {
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@ -418,9 +243,6 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) {
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case MAXWELL3D_REG_INDEX(data_upload): {
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const bool is_last_call = method_call.IsLastCall();
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upload_state.ProcessData(method_call.argument, is_last_call);
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if (is_last_call) {
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dirty.OnMemoryWrite();
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}
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break;
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}
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default:
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@ -727,7 +549,6 @@ void Maxwell3D::FinishCBData() {
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const u32 id = cb_data_state.id;
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memory_manager.WriteBlock(address, cb_data_state.buffer[id].data(), size);
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dirty.OnMemoryWrite();
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cb_data_state.id = null_cb_data;
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cb_data_state.current = null_cb_data;
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@ -1238,79 +1238,6 @@ public:
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State state{};
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struct DirtyRegs {
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static constexpr std::size_t NUM_REGS = 256;
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static_assert(NUM_REGS - 1 <= std::numeric_limits<u8>::max());
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union {
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struct {
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bool null_dirty;
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// Vertex Attributes
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bool vertex_attrib_format;
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// Vertex Arrays
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std::array<bool, 32> vertex_array;
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bool vertex_array_buffers;
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// Vertex Instances
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std::array<bool, 32> vertex_instance;
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bool vertex_instances;
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// Render Targets
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std::array<bool, 8> render_target;
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bool depth_buffer;
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bool render_settings;
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// Shaders
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bool shaders;
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// Rasterizer State
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bool viewport;
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bool clip_coefficient;
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bool cull_mode;
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bool primitive_restart;
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bool depth_test;
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bool stencil_test;
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bool blend_state;
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bool scissor_test;
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bool transform_feedback;
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bool color_mask;
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bool polygon_offset;
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bool depth_bounds_values;
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// Complementary
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bool viewport_transform;
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bool screen_y_control;
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bool memory_general;
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};
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std::array<bool, NUM_REGS> regs;
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};
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void ResetVertexArrays() {
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vertex_array.fill(true);
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vertex_array_buffers = true;
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}
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void ResetRenderTargets() {
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depth_buffer = true;
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render_target.fill(true);
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render_settings = true;
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}
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void OnMemoryWrite() {
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shaders = true;
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memory_general = true;
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ResetRenderTargets();
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ResetVertexArrays();
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}
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} dirty{};
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/// Reads a register value located at the input method address
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u32 GetRegisterValue(u32 method) const;
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@ -1417,8 +1344,6 @@ private:
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/// Retrieves information about a specific TSC entry from the TSC buffer.
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Texture::TSCEntry GetTSCEntry(u32 tsc_index) const;
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void InitDirtySettings();
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/**
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* Call a macro on this engine.
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* @param method Method to call
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@ -56,9 +56,6 @@ void MaxwellDMA::HandleCopy() {
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return;
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}
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// All copies here update the main memory, so mark all rasterizer states as invalid.
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system.GPU().Maxwell3D().dirty.OnMemoryWrite();
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if (regs.exec.is_dst_linear && regs.exec.is_src_linear) {
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// When the enable_2d bit is disabled, the copy is performed as if we were copying a 1D
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// buffer of length `x_count`, otherwise we copy a 2D image of dimensions (x_count,
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@ -117,11 +117,6 @@ GLuint RasterizerOpenGL::SetupVertexFormat() {
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auto& gpu = system.GPU().Maxwell3D();
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const auto& regs = gpu.regs;
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if (!gpu.dirty.vertex_attrib_format) {
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return state.draw.vertex_array;
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}
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gpu.dirty.vertex_attrib_format = false;
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||||
|
||||
MICROPROFILE_SCOPE(OpenGL_VAO);
|
||||
|
||||
auto [iter, is_cache_miss] = vertex_array_cache.try_emplace(regs.vertex_attrib_format);
|
||||
|
|
@ -173,30 +168,18 @@ GLuint RasterizerOpenGL::SetupVertexFormat() {
|
|||
}
|
||||
}
|
||||
|
||||
// Rebinding the VAO invalidates the vertex buffer bindings.
|
||||
gpu.dirty.ResetVertexArrays();
|
||||
|
||||
state.draw.vertex_array = vao_entry.handle;
|
||||
return vao_entry.handle;
|
||||
}
|
||||
|
||||
void RasterizerOpenGL::SetupVertexBuffer(GLuint vao) {
|
||||
auto& gpu = system.GPU().Maxwell3D();
|
||||
if (!gpu.dirty.vertex_array_buffers)
|
||||
return;
|
||||
gpu.dirty.vertex_array_buffers = false;
|
||||
|
||||
const auto& regs = gpu.regs;
|
||||
|
||||
MICROPROFILE_SCOPE(OpenGL_VB);
|
||||
|
||||
// Upload all guest vertex arrays sequentially to our buffer
|
||||
for (u32 index = 0; index < Maxwell::NumVertexArrays; ++index) {
|
||||
if (!gpu.dirty.vertex_array[index])
|
||||
continue;
|
||||
gpu.dirty.vertex_array[index] = false;
|
||||
gpu.dirty.vertex_instance[index] = false;
|
||||
|
||||
const auto& vertex_array = regs.vertex_array[index];
|
||||
if (!vertex_array.IsEnabled())
|
||||
continue;
|
||||
|
|
@ -224,19 +207,10 @@ void RasterizerOpenGL::SetupVertexBuffer(GLuint vao) {
|
|||
|
||||
void RasterizerOpenGL::SetupVertexInstances(GLuint vao) {
|
||||
auto& gpu = system.GPU().Maxwell3D();
|
||||
|
||||
if (!gpu.dirty.vertex_instances)
|
||||
return;
|
||||
gpu.dirty.vertex_instances = false;
|
||||
|
||||
const auto& regs = gpu.regs;
|
||||
|
||||
// Upload all guest vertex arrays sequentially to our buffer
|
||||
for (u32 index = 0; index < Maxwell::NumVertexArrays; ++index) {
|
||||
if (!gpu.dirty.vertex_instance[index])
|
||||
continue;
|
||||
|
||||
gpu.dirty.vertex_instance[index] = false;
|
||||
|
||||
for (u32 index = 0; index < 16; ++index) {
|
||||
if (regs.instanced_arrays.IsInstancingEnabled(index) &&
|
||||
regs.vertex_array[index].divisor != 0) {
|
||||
// Enable vertex buffer instancing with the specified divisor.
|
||||
|
|
@ -334,8 +308,6 @@ void RasterizerOpenGL::SetupShaders(GLenum primitive_mode) {
|
|||
}
|
||||
|
||||
SyncClipEnabled(clip_distances);
|
||||
|
||||
gpu.dirty.shaders = false;
|
||||
}
|
||||
|
||||
std::size_t RasterizerOpenGL::CalculateVertexArraysSize() const {
|
||||
|
|
@ -371,10 +343,6 @@ void RasterizerOpenGL::LoadDiskResources(const std::atomic_bool& stop_loading,
|
|||
void RasterizerOpenGL::ConfigureFramebuffers() {
|
||||
MICROPROFILE_SCOPE(OpenGL_Framebuffer);
|
||||
auto& gpu = system.GPU().Maxwell3D();
|
||||
if (!gpu.dirty.render_settings) {
|
||||
return;
|
||||
}
|
||||
gpu.dirty.render_settings = false;
|
||||
|
||||
texture_cache.GuardRenderTargets(true);
|
||||
|
||||
|
|
@ -453,7 +421,6 @@ void RasterizerOpenGL::Clear() {
|
|||
|
||||
OpenGLState prev_state{OpenGLState::GetCurState()};
|
||||
SCOPE_EXIT({
|
||||
prev_state.AllDirty();
|
||||
prev_state.Apply();
|
||||
});
|
||||
|
||||
|
|
@ -528,7 +495,6 @@ void RasterizerOpenGL::Clear() {
|
|||
clear_state.EmulateViewportWithScissor();
|
||||
}
|
||||
|
||||
clear_state.AllDirty();
|
||||
clear_state.Apply();
|
||||
|
||||
if (use_color) {
|
||||
|
|
@ -631,12 +597,6 @@ void RasterizerOpenGL::Draw(bool is_indexed, bool is_instanced) {
|
|||
bind_ubo_pushbuffer.Bind();
|
||||
bind_ssbo_pushbuffer.Bind();
|
||||
|
||||
if (invalidate) {
|
||||
// As all cached buffers are invalidated, we need to recheck their state.
|
||||
gpu.dirty.ResetVertexArrays();
|
||||
}
|
||||
gpu.dirty.memory_general = false;
|
||||
|
||||
shader_program_manager->ApplyTo(state);
|
||||
state.Apply();
|
||||
|
||||
|
|
@ -1084,14 +1044,8 @@ void RasterizerOpenGL::SyncDepthTestState() {
|
|||
|
||||
void RasterizerOpenGL::SyncStencilTestState() {
|
||||
auto& maxwell3d = system.GPU().Maxwell3D();
|
||||
if (!maxwell3d.dirty.stencil_test) {
|
||||
return;
|
||||
}
|
||||
maxwell3d.dirty.stencil_test = false;
|
||||
|
||||
const auto& regs = maxwell3d.regs;
|
||||
state.stencil.test_enabled = regs.stencil_enable != 0;
|
||||
state.MarkDirtyStencilState();
|
||||
|
||||
if (!regs.stencil_enable) {
|
||||
return;
|
||||
|
|
@ -1130,9 +1084,6 @@ void RasterizerOpenGL::SyncRasterizeEnable(OpenGLState& current_state) {
|
|||
|
||||
void RasterizerOpenGL::SyncColorMask() {
|
||||
auto& maxwell3d = system.GPU().Maxwell3D();
|
||||
if (!maxwell3d.dirty.color_mask) {
|
||||
return;
|
||||
}
|
||||
const auto& regs = maxwell3d.regs;
|
||||
|
||||
const std::size_t count =
|
||||
|
|
@ -1145,9 +1096,6 @@ void RasterizerOpenGL::SyncColorMask() {
|
|||
dest.blue_enabled = (source.B == 0) ? GL_FALSE : GL_TRUE;
|
||||
dest.alpha_enabled = (source.A == 0) ? GL_FALSE : GL_TRUE;
|
||||
}
|
||||
|
||||
state.MarkDirtyColorMask();
|
||||
maxwell3d.dirty.color_mask = false;
|
||||
}
|
||||
|
||||
void RasterizerOpenGL::SyncMultiSampleState() {
|
||||
|
|
@ -1163,9 +1111,6 @@ void RasterizerOpenGL::SyncFragmentColorClampState() {
|
|||
|
||||
void RasterizerOpenGL::SyncBlendState() {
|
||||
auto& maxwell3d = system.GPU().Maxwell3D();
|
||||
if (!maxwell3d.dirty.blend_state) {
|
||||
return;
|
||||
}
|
||||
const auto& regs = maxwell3d.regs;
|
||||
|
||||
state.blend_color.red = regs.blend_color.r;
|
||||
|
|
@ -1189,8 +1134,6 @@ void RasterizerOpenGL::SyncBlendState() {
|
|||
for (std::size_t i = 1; i < Tegra::Engines::Maxwell3D::Regs::NumRenderTargets; i++) {
|
||||
state.blend[i].enabled = false;
|
||||
}
|
||||
maxwell3d.dirty.blend_state = false;
|
||||
state.MarkDirtyBlendState();
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1207,9 +1150,6 @@ void RasterizerOpenGL::SyncBlendState() {
|
|||
blend.src_a_func = MaxwellToGL::BlendFunc(src.factor_source_a);
|
||||
blend.dst_a_func = MaxwellToGL::BlendFunc(src.factor_dest_a);
|
||||
}
|
||||
|
||||
state.MarkDirtyBlendState();
|
||||
maxwell3d.dirty.blend_state = false;
|
||||
}
|
||||
|
||||
void RasterizerOpenGL::SyncLogicOpState() {
|
||||
|
|
@ -1264,9 +1204,6 @@ void RasterizerOpenGL::SyncPointState() {
|
|||
|
||||
void RasterizerOpenGL::SyncPolygonOffset() {
|
||||
auto& maxwell3d = system.GPU().Maxwell3D();
|
||||
if (!maxwell3d.dirty.polygon_offset) {
|
||||
return;
|
||||
}
|
||||
const auto& regs = maxwell3d.regs;
|
||||
|
||||
state.polygon_offset.fill_enable = regs.polygon_offset_fill_enable != 0;
|
||||
|
|
@ -1277,9 +1214,6 @@ void RasterizerOpenGL::SyncPolygonOffset() {
|
|||
state.polygon_offset.units = regs.polygon_offset_units / 2.0f;
|
||||
state.polygon_offset.factor = regs.polygon_offset_factor;
|
||||
state.polygon_offset.clamp = regs.polygon_offset_clamp;
|
||||
|
||||
state.MarkDirtyPolygonOffset();
|
||||
maxwell3d.dirty.polygon_offset = false;
|
||||
}
|
||||
|
||||
void RasterizerOpenGL::SyncAlphaTest() {
|
||||
|
|
|
|||
|
|
@ -623,10 +623,6 @@ bool ShaderCacheOpenGL::GenerateUnspecializedShaders(
|
|||
}
|
||||
|
||||
Shader ShaderCacheOpenGL::GetStageProgram(Maxwell::ShaderProgram program) {
|
||||
if (!system.GPU().Maxwell3D().dirty.shaders) {
|
||||
return last_shaders[static_cast<std::size_t>(program)];
|
||||
}
|
||||
|
||||
auto& memory_manager{system.GPU().MemoryManager()};
|
||||
const GPUVAddr address{GetShaderAddress(system, program)};
|
||||
|
||||
|
|
|
|||
|
|
@ -189,11 +189,6 @@ void OpenGLState::ApplyRasterizerDiscard() {
|
|||
}
|
||||
|
||||
void OpenGLState::ApplyColorMask() {
|
||||
if (!dirty.color_mask) {
|
||||
return;
|
||||
}
|
||||
dirty.color_mask = false;
|
||||
|
||||
for (std::size_t i = 0; i < Maxwell::NumRenderTargets; ++i) {
|
||||
const auto& updated = color_mask[i];
|
||||
auto& current = cur_state.color_mask[i];
|
||||
|
|
@ -232,11 +227,6 @@ void OpenGLState::ApplyPrimitiveRestart() {
|
|||
}
|
||||
|
||||
void OpenGLState::ApplyStencilTest() {
|
||||
if (!dirty.stencil_state) {
|
||||
return;
|
||||
}
|
||||
dirty.stencil_state = false;
|
||||
|
||||
Enable(GL_STENCIL_TEST, cur_state.stencil.test_enabled, stencil.test_enabled);
|
||||
|
||||
const auto ConfigStencil = [](GLenum face, const auto& config, auto& current) {
|
||||
|
|
@ -351,11 +341,6 @@ void OpenGLState::ApplyTargetBlending(std::size_t target, bool force) {
|
|||
}
|
||||
|
||||
void OpenGLState::ApplyBlending() {
|
||||
if (!dirty.blend_state) {
|
||||
return;
|
||||
}
|
||||
dirty.blend_state = false;
|
||||
|
||||
if (independant_blend.enabled) {
|
||||
const bool force = independant_blend.enabled != cur_state.independant_blend.enabled;
|
||||
for (std::size_t target = 0; target < Maxwell::NumRenderTargets; ++target) {
|
||||
|
|
@ -383,11 +368,6 @@ void OpenGLState::ApplyLogicOp() {
|
|||
}
|
||||
|
||||
void OpenGLState::ApplyPolygonOffset() {
|
||||
if (!dirty.polygon_offset) {
|
||||
return;
|
||||
}
|
||||
dirty.polygon_offset = false;
|
||||
|
||||
Enable(GL_POLYGON_OFFSET_FILL, cur_state.polygon_offset.fill_enable,
|
||||
polygon_offset.fill_enable);
|
||||
Enable(GL_POLYGON_OFFSET_LINE, cur_state.polygon_offset.line_enable,
|
||||
|
|
|
|||
|
|
@ -212,39 +212,8 @@ public:
|
|||
/// Viewport does not affects glClearBuffer so emulate viewport using scissor test
|
||||
void EmulateViewportWithScissor();
|
||||
|
||||
void MarkDirtyBlendState() {
|
||||
dirty.blend_state = true;
|
||||
}
|
||||
|
||||
void MarkDirtyStencilState() {
|
||||
dirty.stencil_state = true;
|
||||
}
|
||||
|
||||
void MarkDirtyPolygonOffset() {
|
||||
dirty.polygon_offset = true;
|
||||
}
|
||||
|
||||
void MarkDirtyColorMask() {
|
||||
dirty.color_mask = true;
|
||||
}
|
||||
|
||||
void AllDirty() {
|
||||
dirty.blend_state = true;
|
||||
dirty.stencil_state = true;
|
||||
dirty.polygon_offset = true;
|
||||
dirty.color_mask = true;
|
||||
}
|
||||
|
||||
private:
|
||||
static OpenGLState cur_state;
|
||||
|
||||
struct {
|
||||
bool blend_state;
|
||||
bool stencil_state;
|
||||
bool viewport_state;
|
||||
bool polygon_offset;
|
||||
bool color_mask;
|
||||
} dirty{};
|
||||
};
|
||||
static_assert(std::is_trivially_copyable_v<OpenGLState>);
|
||||
|
||||
|
|
|
|||
|
|
@ -522,7 +522,6 @@ void TextureCacheOpenGL::ImageBlit(View& src_view, View& dst_view,
|
|||
|
||||
OpenGLState prev_state{OpenGLState::GetCurState()};
|
||||
SCOPE_EXIT({
|
||||
prev_state.AllDirty();
|
||||
prev_state.Apply();
|
||||
});
|
||||
|
||||
|
|
@ -530,7 +529,6 @@ void TextureCacheOpenGL::ImageBlit(View& src_view, View& dst_view,
|
|||
state.draw.read_framebuffer = src_framebuffer.handle;
|
||||
state.draw.draw_framebuffer = dst_framebuffer.handle;
|
||||
state.framebuffer_srgb.enabled = dst_params.srgb_conversion;
|
||||
state.AllDirty();
|
||||
state.Apply();
|
||||
|
||||
u32 buffers{};
|
||||
|
|
|
|||
|
|
@ -311,11 +311,6 @@ void RendererOpenGL::SwapBuffers(const Tegra::FramebufferConfig* framebuffer) {
|
|||
return;
|
||||
}
|
||||
|
||||
// Maintain the rasterizer's state as a priority
|
||||
OpenGLState prev_state = OpenGLState::GetCurState();
|
||||
state.AllDirty();
|
||||
state.Apply();
|
||||
|
||||
PrepareRendertarget(framebuffer);
|
||||
RenderScreenshot();
|
||||
|
||||
|
|
@ -368,10 +363,6 @@ void RendererOpenGL::SwapBuffers(const Tegra::FramebufferConfig* framebuffer) {
|
|||
m_current_frame++;
|
||||
rasterizer->TickFrame();
|
||||
}
|
||||
|
||||
// Restore the rasterizer state
|
||||
prev_state.AllDirty();
|
||||
prev_state.Apply();
|
||||
}
|
||||
|
||||
void RendererOpenGL::PrepareRendertarget(const Tegra::FramebufferConfig* framebuffer) {
|
||||
|
|
@ -445,7 +436,6 @@ void RendererOpenGL::InitOpenGLObjects() {
|
|||
// Link shaders and get variable locations
|
||||
shader.CreateFromSource(vertex_shader, nullptr, fragment_shader);
|
||||
state.draw.shader_program = shader.handle;
|
||||
state.AllDirty();
|
||||
state.Apply();
|
||||
|
||||
// Generate VBO handle for drawing
|
||||
|
|
@ -580,14 +570,12 @@ void RendererOpenGL::DrawScreenTriangles(const ScreenInfo& screen_info, float x,
|
|||
|
||||
state.textures[0] = screen_info.display_texture;
|
||||
state.framebuffer_srgb.enabled = screen_info.display_srgb;
|
||||
state.AllDirty();
|
||||
state.Apply();
|
||||
glNamedBufferSubData(vertex_buffer.handle, 0, sizeof(vertices), std::data(vertices));
|
||||
glDrawArrays(GL_TRIANGLE_STRIP, 0, 4);
|
||||
// Restore default state
|
||||
state.framebuffer_srgb.enabled = false;
|
||||
state.textures[0] = 0;
|
||||
state.AllDirty();
|
||||
state.Apply();
|
||||
}
|
||||
|
||||
|
|
@ -658,7 +646,6 @@ void RendererOpenGL::RenderScreenshot() {
|
|||
GLuint old_read_fb = state.draw.read_framebuffer;
|
||||
GLuint old_draw_fb = state.draw.draw_framebuffer;
|
||||
state.draw.read_framebuffer = state.draw.draw_framebuffer = screenshot_framebuffer.handle;
|
||||
state.AllDirty();
|
||||
state.Apply();
|
||||
|
||||
Layout::FramebufferLayout layout{renderer_settings.screenshot_framebuffer_layout};
|
||||
|
|
@ -678,7 +665,6 @@ void RendererOpenGL::RenderScreenshot() {
|
|||
screenshot_framebuffer.Release();
|
||||
state.draw.read_framebuffer = old_read_fb;
|
||||
state.draw.draw_framebuffer = old_draw_fb;
|
||||
state.AllDirty();
|
||||
state.Apply();
|
||||
glDeleteRenderbuffers(1, &renderbuffer);
|
||||
|
||||
|
|
|
|||
|
|
@ -172,11 +172,6 @@ VKPipelineCache::~VKPipelineCache() = default;
|
|||
|
||||
std::array<Shader, Maxwell::MaxShaderProgram> VKPipelineCache::GetShaders() {
|
||||
const auto& gpu = system.GPU().Maxwell3D();
|
||||
auto& dirty = system.GPU().Maxwell3D().dirty.shaders;
|
||||
if (!dirty) {
|
||||
return last_shaders;
|
||||
}
|
||||
dirty = false;
|
||||
|
||||
std::array<Shader, Maxwell::MaxShaderProgram> shaders;
|
||||
for (std::size_t index = 0; index < Maxwell::MaxShaderProgram; ++index) {
|
||||
|
|
|
|||
|
|
@ -568,9 +568,7 @@ void RasterizerVulkan::FlushWork() {
|
|||
|
||||
RasterizerVulkan::Texceptions RasterizerVulkan::UpdateAttachments() {
|
||||
MICROPROFILE_SCOPE(Vulkan_RenderTargets);
|
||||
auto& dirty = system.GPU().Maxwell3D().dirty;
|
||||
const bool update_rendertargets = dirty.render_settings;
|
||||
dirty.render_settings = false;
|
||||
constexpr bool update_rendertargets = true;
|
||||
|
||||
texture_cache.GuardRenderTargets(true);
|
||||
|
||||
|
|
@ -973,10 +971,6 @@ void RasterizerVulkan::SetupImage(const Tegra::Texture::TICEntry& tic, const Ima
|
|||
}
|
||||
|
||||
void RasterizerVulkan::UpdateViewportsState(Tegra::Engines::Maxwell3D& gpu) {
|
||||
if (!gpu.dirty.viewport_transform && scheduler.TouchViewports()) {
|
||||
return;
|
||||
}
|
||||
gpu.dirty.viewport_transform = false;
|
||||
const auto& regs = gpu.regs;
|
||||
const std::array viewports{
|
||||
GetViewportState(device, regs, 0), GetViewportState(device, regs, 1),
|
||||
|
|
@ -993,10 +987,6 @@ void RasterizerVulkan::UpdateViewportsState(Tegra::Engines::Maxwell3D& gpu) {
|
|||
}
|
||||
|
||||
void RasterizerVulkan::UpdateScissorsState(Tegra::Engines::Maxwell3D& gpu) {
|
||||
if (!gpu.dirty.scissor_test && scheduler.TouchScissors()) {
|
||||
return;
|
||||
}
|
||||
gpu.dirty.scissor_test = false;
|
||||
const auto& regs = gpu.regs;
|
||||
const std::array scissors = {
|
||||
GetScissorState(regs, 0), GetScissorState(regs, 1), GetScissorState(regs, 2),
|
||||
|
|
@ -1011,10 +1001,6 @@ void RasterizerVulkan::UpdateScissorsState(Tegra::Engines::Maxwell3D& gpu) {
|
|||
}
|
||||
|
||||
void RasterizerVulkan::UpdateDepthBias(Tegra::Engines::Maxwell3D& gpu) {
|
||||
if (!gpu.dirty.polygon_offset && scheduler.TouchDepthBias()) {
|
||||
return;
|
||||
}
|
||||
gpu.dirty.polygon_offset = false;
|
||||
const auto& regs = gpu.regs;
|
||||
scheduler.Record([constant = regs.polygon_offset_units, clamp = regs.polygon_offset_clamp,
|
||||
factor = regs.polygon_offset_factor](auto cmdbuf, auto& dld) {
|
||||
|
|
@ -1023,10 +1009,6 @@ void RasterizerVulkan::UpdateDepthBias(Tegra::Engines::Maxwell3D& gpu) {
|
|||
}
|
||||
|
||||
void RasterizerVulkan::UpdateBlendConstants(Tegra::Engines::Maxwell3D& gpu) {
|
||||
if (!gpu.dirty.blend_state && scheduler.TouchBlendConstants()) {
|
||||
return;
|
||||
}
|
||||
gpu.dirty.blend_state = false;
|
||||
const std::array blend_color = {gpu.regs.blend_color.r, gpu.regs.blend_color.g,
|
||||
gpu.regs.blend_color.b, gpu.regs.blend_color.a};
|
||||
scheduler.Record([blend_color](auto cmdbuf, auto& dld) {
|
||||
|
|
@ -1035,20 +1017,12 @@ void RasterizerVulkan::UpdateBlendConstants(Tegra::Engines::Maxwell3D& gpu) {
|
|||
}
|
||||
|
||||
void RasterizerVulkan::UpdateDepthBounds(Tegra::Engines::Maxwell3D& gpu) {
|
||||
if (!gpu.dirty.depth_bounds_values && scheduler.TouchDepthBounds()) {
|
||||
return;
|
||||
}
|
||||
gpu.dirty.depth_bounds_values = false;
|
||||
const auto& regs = gpu.regs;
|
||||
scheduler.Record([min = regs.depth_bounds[0], max = regs.depth_bounds[1]](
|
||||
auto cmdbuf, auto& dld) { cmdbuf.setDepthBounds(min, max, dld); });
|
||||
}
|
||||
|
||||
void RasterizerVulkan::UpdateStencilFaces(Tegra::Engines::Maxwell3D& gpu) {
|
||||
if (!gpu.dirty.stencil_test && scheduler.TouchStencilValues()) {
|
||||
return;
|
||||
}
|
||||
gpu.dirty.stencil_test = false;
|
||||
const auto& regs = gpu.regs;
|
||||
if (regs.stencil_two_side_enable) {
|
||||
// Separate values per face
|
||||
|
|
|
|||
|
|
@ -143,11 +143,6 @@ public:
|
|||
std::lock_guard lock{mutex};
|
||||
auto& maxwell3d = system.GPU().Maxwell3D();
|
||||
|
||||
if (!maxwell3d.dirty.depth_buffer) {
|
||||
return depth_buffer.view;
|
||||
}
|
||||
maxwell3d.dirty.depth_buffer = false;
|
||||
|
||||
const auto& regs{maxwell3d.regs};
|
||||
const auto gpu_addr{regs.zeta.Address()};
|
||||
if (!gpu_addr || !regs.zeta_enable) {
|
||||
|
|
@ -175,10 +170,6 @@ public:
|
|||
std::lock_guard lock{mutex};
|
||||
ASSERT(index < Tegra::Engines::Maxwell3D::Regs::NumRenderTargets);
|
||||
auto& maxwell3d = system.GPU().Maxwell3D();
|
||||
if (!maxwell3d.dirty.render_target[index]) {
|
||||
return render_targets[index].view;
|
||||
}
|
||||
maxwell3d.dirty.render_target[index] = false;
|
||||
|
||||
const auto& regs{maxwell3d.regs};
|
||||
if (index >= regs.rt_control.count || regs.rt[index].Address() == 0 ||
|
||||
|
|
@ -319,16 +310,7 @@ protected:
|
|||
// and reading it from a separate buffer.
|
||||
virtual void BufferCopy(TSurface& src_surface, TSurface& dst_surface) = 0;
|
||||
|
||||
void ManageRenderTargetUnregister(TSurface& surface) {
|
||||
auto& maxwell3d = system.GPU().Maxwell3D();
|
||||
const u32 index = surface->GetRenderTarget();
|
||||
if (index == DEPTH_RT) {
|
||||
maxwell3d.dirty.depth_buffer = true;
|
||||
} else {
|
||||
maxwell3d.dirty.render_target[index] = true;
|
||||
}
|
||||
maxwell3d.dirty.render_settings = true;
|
||||
}
|
||||
void ManageRenderTargetUnregister([[maybe_unused]] TSurface& surface) {}
|
||||
|
||||
void Register(TSurface surface) {
|
||||
const GPUVAddr gpu_addr = surface->GetGpuAddr();
|
||||
|
|
|
|||
Reference in New Issue