shader_bytecode: Decode instructions based on bit strings.
This commit is contained in:
bunnei
parent
8ac3a3f45e
commit
9f6d305eab
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@ -4,10 +4,16 @@
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#pragma once
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#include <bitset>
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#include <cstring>
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#include <map>
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#include <string>
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#include <vector>
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#include <boost/optional.hpp>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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namespace Tegra {
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namespace Shader {
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@ -89,188 +95,12 @@ union Uniform {
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BitField<34, 5, u64> index;
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};
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union OpCode {
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enum class Id : u64 {
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TEXS = 0x6C,
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IPA = 0xE0,
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FMUL32_IMM = 0x1E,
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FFMA_IMM = 0x65,
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FFMA_CR = 0x93,
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FFMA_RC = 0xA3,
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FFMA_RR = 0xB3,
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FADD_C = 0x98B,
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FMUL_C = 0x98D,
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MUFU = 0xA10,
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FADD_R = 0xB8B,
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FMUL_R = 0xB8D,
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LD_A = 0x1DFB,
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ST_A = 0x1DFE,
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FSETP_R = 0x5BB,
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FSETP_C = 0x4BB,
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FSETP_IMM = 0x36B,
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FSETP_NEG_IMM = 0x37B,
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EXIT = 0xE30,
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KIL = 0xE33,
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FMUL_IMM = 0x70D,
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FMUL_IMM_x = 0x72D,
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FADD_IMM = 0x70B,
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FADD_IMM_x = 0x72B,
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};
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enum class Type {
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Trivial,
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Arithmetic,
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Ffma,
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Flow,
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Memory,
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FloatPredicate,
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Unknown,
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};
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struct Info {
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Type type;
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std::string name;
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};
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OpCode() = default;
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constexpr OpCode(Id value) : value(static_cast<u64>(value)) {}
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constexpr OpCode(u64 value) : value{value} {}
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constexpr Id EffectiveOpCode() const {
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switch (op1) {
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case Id::TEXS:
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return op1;
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}
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switch (op2) {
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case Id::IPA:
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case Id::FMUL32_IMM:
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return op2;
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}
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switch (op3) {
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case Id::FFMA_IMM:
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case Id::FFMA_CR:
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case Id::FFMA_RC:
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case Id::FFMA_RR:
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return op3;
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}
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switch (op4) {
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case Id::EXIT:
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case Id::FSETP_R:
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case Id::FSETP_C:
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case Id::KIL:
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return op4;
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case Id::FSETP_IMM:
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case Id::FSETP_NEG_IMM:
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return Id::FSETP_IMM;
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}
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switch (op5) {
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case Id::MUFU:
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case Id::LD_A:
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case Id::ST_A:
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case Id::FADD_R:
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case Id::FADD_C:
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case Id::FMUL_R:
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case Id::FMUL_C:
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return op5;
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case Id::FMUL_IMM:
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case Id::FMUL_IMM_x:
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return Id::FMUL_IMM;
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case Id::FADD_IMM:
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case Id::FADD_IMM_x:
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return Id::FADD_IMM;
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}
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return static_cast<Id>(value);
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}
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static const Info& GetInfo(const OpCode& opcode) {
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static const std::map<Id, Info> info_table{BuildInfoTable()};
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const auto& search{info_table.find(opcode.EffectiveOpCode())};
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if (search != info_table.end()) {
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return search->second;
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}
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static const Info unknown{Type::Unknown, "UNK"};
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return unknown;
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}
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constexpr operator Id() const {
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return static_cast<Id>(value);
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}
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constexpr OpCode operator<<(size_t bits) const {
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return value << bits;
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}
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constexpr OpCode operator>>(size_t bits) const {
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return value >> bits;
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}
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template <typename T>
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constexpr u64 operator-(const T& oth) const {
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return value - oth;
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}
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constexpr u64 operator&(const OpCode& oth) const {
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return value & oth.value;
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}
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constexpr u64 operator~() const {
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return ~value;
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}
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static std::map<Id, Info> BuildInfoTable() {
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std::map<Id, Info> info_table;
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info_table[Id::TEXS] = {Type::Memory, "texs"};
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info_table[Id::LD_A] = {Type::Memory, "ld_a"};
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info_table[Id::ST_A] = {Type::Memory, "st_a"};
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info_table[Id::MUFU] = {Type::Arithmetic, "mufu"};
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info_table[Id::FFMA_IMM] = {Type::Ffma, "ffma_imm"};
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info_table[Id::FFMA_CR] = {Type::Ffma, "ffma_cr"};
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info_table[Id::FFMA_RC] = {Type::Ffma, "ffma_rc"};
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info_table[Id::FFMA_RR] = {Type::Ffma, "ffma_rr"};
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info_table[Id::FADD_R] = {Type::Arithmetic, "fadd_r"};
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info_table[Id::FADD_C] = {Type::Arithmetic, "fadd_c"};
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info_table[Id::FADD_IMM] = {Type::Arithmetic, "fadd_imm"};
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info_table[Id::FMUL_R] = {Type::Arithmetic, "fmul_r"};
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info_table[Id::FMUL_C] = {Type::Arithmetic, "fmul_c"};
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info_table[Id::FMUL_IMM] = {Type::Arithmetic, "fmul_imm"};
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info_table[Id::FMUL32_IMM] = {Type::Arithmetic, "fmul32_imm"};
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info_table[Id::FSETP_C] = {Type::FloatPredicate, "fsetp_c"};
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info_table[Id::FSETP_R] = {Type::FloatPredicate, "fsetp_r"};
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info_table[Id::FSETP_IMM] = {Type::FloatPredicate, "fsetp_imm"};
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info_table[Id::EXIT] = {Type::Trivial, "exit"};
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info_table[Id::IPA] = {Type::Trivial, "ipa"};
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info_table[Id::KIL] = {Type::Flow, "kil"};
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return info_table;
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}
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BitField<57, 7, Id> op1;
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BitField<56, 8, Id> op2;
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BitField<55, 9, Id> op3;
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BitField<52, 12, Id> op4;
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BitField<51, 13, Id> op5;
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u64 value{};
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};
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static_assert(sizeof(OpCode) == 0x8, "Incorrect structure size");
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} // namespace Shader
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} // namespace Tegra
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namespace std {
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// TODO(bunne): The below is forbidden by the C++ standard, but works fine. See #330.
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// TODO(bunnei): The below is forbidden by the C++ standard, but works fine. See #330.
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template <>
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struct make_unsigned<Tegra::Shader::Attribute> {
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using type = Tegra::Shader::Attribute;
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@ -281,11 +111,6 @@ struct make_unsigned<Tegra::Shader::Register> {
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using type = Tegra::Shader::Register;
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};
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template <>
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struct make_unsigned<Tegra::Shader::OpCode> {
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using type = Tegra::Shader::OpCode;
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};
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} // namespace std
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namespace Tegra {
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@ -324,11 +149,12 @@ enum class SubOp : u64 {
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union Instruction {
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Instruction& operator=(const Instruction& instr) {
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hex = instr.hex;
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value = instr.value;
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return *this;
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}
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OpCode opcode;
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constexpr Instruction(u64 value) : value{value} {}
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BitField<0, 8, Register> gpr0;
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BitField<8, 8, Register> gpr8;
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union {
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@ -340,6 +166,7 @@ union Instruction {
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BitField<20, 7, SubOp> sub_op;
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BitField<28, 8, Register> gpr28;
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BitField<39, 8, Register> gpr39;
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BitField<48, 16, u64> opcode;
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union {
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BitField<20, 19, u64> imm20_19;
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@ -395,11 +222,171 @@ union Instruction {
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Uniform uniform;
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Sampler sampler;
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u64 hex;
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u64 value;
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};
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static_assert(sizeof(Instruction) == 0x8, "Incorrect structure size");
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static_assert(std::is_standard_layout<Instruction>::value,
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"Structure does not have standard layout");
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class OpCode {
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public:
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enum class Id {
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KIL,
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LD_A,
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ST_A,
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TEXS,
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EXIT,
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IPA,
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FFMA_IMM,
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FFMA_CR,
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FFMA_RC,
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FFMA_RR,
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FADD_C,
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FADD_R,
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FADD_IMM,
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FMUL_C,
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FMUL_R,
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FMUL_IMM,
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FMUL32_IMM,
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MUFU,
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FSETP_R,
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FSETP_C,
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FSETP_IMM,
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};
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enum class Type {
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Trivial,
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Arithmetic,
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Ffma,
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Flow,
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Memory,
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FloatPredicate,
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Unknown,
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};
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class Matcher {
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public:
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Matcher(const char* const name, u16 mask, u16 expected, OpCode::Id id, OpCode::Type type)
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: name{name}, mask{mask}, expected{expected}, id{id}, type{type} {}
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const char* GetName() const {
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return name;
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}
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u16 GetMask() const {
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return mask;
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}
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Id GetId() const {
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return id;
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}
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Type GetType() const {
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return type;
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}
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/**
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* Tests to see if the given instruction is the instruction this matcher represents.
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* @param instruction The instruction to test
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* @returns true if the given instruction matches.
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*/
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bool Matches(u16 instruction) const {
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return (instruction & mask) == expected;
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}
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private:
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const char* name;
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u16 mask;
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u16 expected;
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Id id;
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Type type;
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};
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static boost::optional<const Matcher&> Decode(Instruction instr) {
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static const auto table{GetDecodeTable()};
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const auto matches_instruction = [instr](const auto& matcher) {
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return matcher.Matches(static_cast<u16>(instr.opcode));
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};
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auto iter = std::find_if(table.begin(), table.end(), matches_instruction);
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return iter != table.end() ? boost::optional<const Matcher&>(*iter) : boost::none;
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}
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private:
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struct Detail {
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private:
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static constexpr size_t opcode_bitsize = 16;
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/**
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* Generates the mask and the expected value after masking from a given bitstring.
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* A '0' in a bitstring indicates that a zero must be present at that bit position.
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* A '1' in a bitstring indicates that a one must be present at that bit position.
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*/
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static auto GetMaskAndExpect(const char* const bitstring) {
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u16 mask = 0, expect = 0;
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for (size_t i = 0; i < opcode_bitsize; i++) {
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const size_t bit_position = opcode_bitsize - i - 1;
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switch (bitstring[i]) {
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case '0':
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mask |= 1 << bit_position;
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break;
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case '1':
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expect |= 1 << bit_position;
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mask |= 1 << bit_position;
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break;
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default:
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// Ignore
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break;
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}
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}
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return std::make_tuple(mask, expect);
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}
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public:
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/// Creates a matcher that can match and parse instructions based on bitstring.
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static auto GetMatcher(const char* const bitstring, OpCode::Id op, OpCode::Type type,
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const char* const name) {
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const auto mask_expect = GetMaskAndExpect(bitstring);
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return Matcher(name, std::get<0>(mask_expect), std::get<1>(mask_expect), op, type);
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}
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};
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static std::vector<Matcher> GetDecodeTable() {
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std::vector<Matcher> table = {
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#define INST(bitstring, op, type, name) Detail::GetMatcher(bitstring, op, type, name)
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INST("111000110011----", Id::KIL, Type::Flow, "KIL"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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INST("1110111111110---", Id::ST_A, Type::Memory, "ST_A"),
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INST("1101100---------", Id::TEXS, Type::Memory, "TEXS"),
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INST("111000110000----", Id::EXIT, Type::Trivial, "EXIT"),
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INST("11100000--------", Id::IPA, Type::Trivial, "IPA"),
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INST("001100101-------", Id::FFMA_IMM, Type::Ffma, "FFMA_IMM"),
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INST("010010011-------", Id::FFMA_CR, Type::Ffma, "FFMA_CR"),
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INST("010100011-------", Id::FFMA_RC, Type::Ffma, "FFMA_RC"),
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INST("010110011-------", Id::FFMA_RR, Type::Ffma, "FFMA_RR"),
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INST("0100110001011---", Id::FADD_C, Type::Arithmetic, "FADD_C"),
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INST("0101110001011---", Id::FADD_R, Type::Arithmetic, "FADD_R"),
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INST("0011100-01011---", Id::FADD_IMM, Type::Arithmetic, "FADD_IMM"),
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INST("0100110001101---", Id::FMUL_C, Type::Arithmetic, "FMUL_C"),
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INST("0101110001101---", Id::FMUL_R, Type::Arithmetic, "FMUL_R"),
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INST("0011100-01101---", Id::FMUL_IMM, Type::Arithmetic, "FMUL_IMM"),
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INST("00011110--------", Id::FMUL32_IMM, Type::Arithmetic, "FMUL32_IMM"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("010110111011----", Id::FSETP_R, Type::FloatPredicate, "FSETP_R"),
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INST("010010111011----", Id::FSETP_C, Type::FloatPredicate, "FSETP_C"),
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INST("0011011-1011----", Id::FSETP_IMM, Type::FloatPredicate, "FSETP_IMM"),
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};
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#undef INST
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std::stable_sort(table.begin(), table.end(), [](const auto& a, const auto& b) {
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// If a matcher has more bits in its mask it is more specific, so it
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// should come first.
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return std::bitset<16>(a.GetMask()).count() > std::bitset<16>(b.GetMask()).count();
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});
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return table;
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}
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};
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} // namespace Shader
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} // namespace Tegra
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@ -97,13 +97,14 @@ private:
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return exit_method;
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for (u32 offset = begin; offset != end && offset != PROGRAM_END; ++offset) {
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const Instruction instr = {program_code[offset]};
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switch (instr.opcode.EffectiveOpCode()) {
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if (const auto opcode = OpCode::Decode({program_code[offset]})) {
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switch (opcode->GetId()) {
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case OpCode::Id::EXIT: {
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return exit_method = ExitMethod::AlwaysEnd;
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}
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}
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}
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}
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return exit_method = ExitMethod::AlwaysReturn;
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}
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};
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@ -332,12 +333,20 @@ private:
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*/
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u32 CompileInstr(u32 offset) {
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// Ignore sched instructions when generating code.
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if (IsSchedInstruction(offset))
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if (IsSchedInstruction(offset)) {
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return offset + 1;
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}
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const Instruction instr = {program_code[offset]};
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const auto opcode = OpCode::Decode(instr);
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shader.AddLine("// " + std::to_string(offset) + ": " + OpCode::GetInfo(instr.opcode).name);
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// Decoding failure
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if (!opcode) {
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NGLOG_CRITICAL(HW_GPU, "Unhandled instruction: {}", instr.value);
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UNREACHABLE();
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}
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shader.AddLine("// " + std::to_string(offset) + ": " + opcode->GetName());
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using Tegra::Shader::Pred;
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ASSERT_MSG(instr.pred.full_pred != Pred::NeverExecute,
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@ -349,7 +358,7 @@ private:
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++shader.scope;
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}
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switch (OpCode::GetInfo(instr.opcode).type) {
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switch (opcode->GetType()) {
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case OpCode::Type::Arithmetic: {
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std::string dest = GetRegister(instr.gpr0);
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std::string op_a = instr.alu.negate_a ? "-" : "";
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@ -374,7 +383,7 @@ private:
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op_b = "abs(" + op_b + ")";
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}
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switch (instr.opcode.EffectiveOpCode()) {
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switch (opcode->GetId()) {
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case OpCode::Id::FMUL_C:
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case OpCode::Id::FMUL_R:
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case OpCode::Id::FMUL_IMM: {
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@ -424,8 +433,8 @@ private:
|
|||
}
|
||||
default: {
|
||||
NGLOG_CRITICAL(HW_GPU, "Unhandled arithmetic instruction: {} ({}): {}",
|
||||
static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
|
||||
OpCode::GetInfo(instr.opcode).name, instr.hex);
|
||||
static_cast<unsigned>(opcode->GetId()), opcode->GetName(),
|
||||
instr.value);
|
||||
UNREACHABLE();
|
||||
}
|
||||
}
|
||||
|
|
@ -437,7 +446,7 @@ private:
|
|||
std::string op_b = instr.ffma.negate_b ? "-" : "";
|
||||
std::string op_c = instr.ffma.negate_c ? "-" : "";
|
||||
|
||||
switch (instr.opcode.EffectiveOpCode()) {
|
||||
switch (opcode->GetId()) {
|
||||
case OpCode::Id::FFMA_CR: {
|
||||
op_b += GetUniform(instr.uniform);
|
||||
op_c += GetRegister(instr.gpr39);
|
||||
|
|
@ -460,8 +469,8 @@ private:
|
|||
}
|
||||
default: {
|
||||
NGLOG_CRITICAL(HW_GPU, "Unhandled FFMA instruction: {} ({}): {}",
|
||||
static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
|
||||
OpCode::GetInfo(instr.opcode).name, instr.hex);
|
||||
static_cast<unsigned>(opcode->GetId()), opcode->GetName(),
|
||||
instr.value);
|
||||
UNREACHABLE();
|
||||
}
|
||||
}
|
||||
|
|
@ -473,7 +482,7 @@ private:
|
|||
std::string gpr0 = GetRegister(instr.gpr0);
|
||||
const Attribute::Index attribute = instr.attribute.fmt20.index;
|
||||
|
||||
switch (instr.opcode.EffectiveOpCode()) {
|
||||
switch (opcode->GetId()) {
|
||||
case OpCode::Id::LD_A: {
|
||||
ASSERT_MSG(instr.attribute.fmt20.size == 0, "untested");
|
||||
SetDest(instr.attribute.fmt20.element, gpr0, GetInputAttribute(attribute), 1, 4);
|
||||
|
|
@ -505,8 +514,8 @@ private:
|
|||
}
|
||||
default: {
|
||||
NGLOG_CRITICAL(HW_GPU, "Unhandled memory instruction: {} ({}): {}",
|
||||
static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
|
||||
OpCode::GetInfo(instr.opcode).name, instr.hex);
|
||||
static_cast<unsigned>(opcode->GetId()), opcode->GetName(),
|
||||
instr.value);
|
||||
UNREACHABLE();
|
||||
}
|
||||
}
|
||||
|
|
@ -564,7 +573,7 @@ private:
|
|||
break;
|
||||
}
|
||||
default: {
|
||||
switch (instr.opcode.EffectiveOpCode()) {
|
||||
switch (opcode->GetId()) {
|
||||
case OpCode::Id::EXIT: {
|
||||
ASSERT_MSG(instr.pred.pred_index == static_cast<u64>(Pred::UnusedIndex),
|
||||
"Predicated exits not implemented");
|
||||
|
|
@ -584,8 +593,8 @@ private:
|
|||
}
|
||||
default: {
|
||||
NGLOG_CRITICAL(HW_GPU, "Unhandled instruction: {} ({}): {}",
|
||||
static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
|
||||
OpCode::GetInfo(instr.opcode).name, instr.hex);
|
||||
static_cast<unsigned>(opcode->GetId()), opcode->GetName(),
|
||||
instr.value);
|
||||
UNREACHABLE();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Reference in New Issue