Merge pull request #494 from bunnei/shader-tex
gl_shader_decompiler: Implement TEX, fixes for TEXS.
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commit
bb9d39b8fe
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@ -261,6 +261,19 @@ union Instruction {
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BitField<50, 1, u64> saturate_a;
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BitField<50, 1, u64> saturate_a;
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} conversion;
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} conversion;
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union {
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BitField<31, 4, u64> component_mask;
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bool IsComponentEnabled(size_t component) const {
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return ((1 << component) & component_mask) != 0;
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}
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} tex;
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union {
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// TODO(bunnei): This is just a guess, needs to be verified
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BitField<52, 1, u64> enable_g_component;
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} texs;
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BitField<61, 1, u64> is_b_imm;
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BitField<61, 1, u64> is_b_imm;
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BitField<60, 1, u64> is_b_gpr;
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BitField<60, 1, u64> is_b_gpr;
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BitField<59, 1, u64> is_c_gpr;
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BitField<59, 1, u64> is_c_gpr;
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@ -281,6 +294,7 @@ public:
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KIL,
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KIL,
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LD_A,
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LD_A,
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ST_A,
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ST_A,
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TEX,
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TEXQ, // Texture Query
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TEXQ, // Texture Query
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TEXS, // Texture Fetch with scalar/non-vec4 source/destinations
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TEXS, // Texture Fetch with scalar/non-vec4 source/destinations
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TLDS, // Texture Load with scalar/non-vec4 source/destinations
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TLDS, // Texture Load with scalar/non-vec4 source/destinations
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@ -444,6 +458,7 @@ private:
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INST("111000110011----", Id::KIL, Type::Flow, "KIL"),
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INST("111000110011----", Id::KIL, Type::Flow, "KIL"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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INST("1110111111110---", Id::ST_A, Type::Memory, "ST_A"),
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INST("1110111111110---", Id::ST_A, Type::Memory, "ST_A"),
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INST("1100000000111---", Id::TEX, Type::Memory, "TEX"),
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INST("1101111101001---", Id::TEXQ, Type::Memory, "TEXQ"),
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INST("1101111101001---", Id::TEXQ, Type::Memory, "TEXQ"),
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INST("1101100---------", Id::TEXS, Type::Memory, "TEXS"),
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INST("1101100---------", Id::TEXS, Type::Memory, "TEXS"),
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INST("1101101---------", Id::TLDS, Type::Memory, "TLDS"),
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INST("1101101---------", Id::TLDS, Type::Memory, "TLDS"),
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@ -896,6 +896,32 @@ private:
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instr.gpr0);
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instr.gpr0);
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break;
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break;
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}
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}
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case OpCode::Id::TEX: {
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ASSERT_MSG(instr.attribute.fmt20.size == 4, "untested");
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const std::string op_a = regs.GetRegisterAsFloat(instr.gpr8);
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const std::string op_b = regs.GetRegisterAsFloat(instr.gpr8.Value() + 1);
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const std::string sampler = GetSampler(instr.sampler);
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const std::string coord = "vec2 coords = vec2(" + op_a + ", " + op_b + ");";
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// Add an extra scope and declare the texture coords inside to prevent overwriting
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// them in case they are used as outputs of the texs instruction.
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shader.AddLine("{");
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++shader.scope;
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shader.AddLine(coord);
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const std::string texture = "texture(" + sampler + ", coords)";
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size_t dest_elem{};
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for (size_t elem = 0; elem < instr.attribute.fmt20.size; ++elem) {
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if (!instr.tex.IsComponentEnabled(elem)) {
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// Skip disabled components
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continue;
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}
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regs.SetRegisterToFloat(instr.gpr0, elem, texture, 1, 4, false, dest_elem);
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++dest_elem;
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}
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--shader.scope;
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shader.AddLine("}");
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break;
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}
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case OpCode::Id::TEXS: {
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case OpCode::Id::TEXS: {
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ASSERT_MSG(instr.attribute.fmt20.size == 4, "untested");
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ASSERT_MSG(instr.attribute.fmt20.size == 4, "untested");
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const std::string op_a = regs.GetRegisterAsFloat(instr.gpr8);
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const std::string op_a = regs.GetRegisterAsFloat(instr.gpr8);
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@ -908,8 +934,23 @@ private:
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++shader.scope;
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++shader.scope;
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shader.AddLine(coord);
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shader.AddLine(coord);
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const std::string texture = "texture(" + sampler + ", coords)";
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const std::string texture = "texture(" + sampler + ", coords)";
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for (unsigned elem = 0; elem < instr.attribute.fmt20.size; ++elem) {
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regs.SetRegisterToFloat(instr.gpr0, elem, texture, 1, 4, false, elem);
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// TEXS has two destination registers. RG goes into gpr0+0 and gpr0+1, and BA goes
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// into gpr28+0 and gpr28+1
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size_t offset{};
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for (const auto& dest : {instr.gpr0.Value(), instr.gpr28.Value()}) {
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for (unsigned elem = 0; elem < 2; ++elem) {
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if (dest + elem >= Register::ZeroIndex) {
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// Skip invalid register values
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break;
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}
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regs.SetRegisterToFloat(dest, elem + offset, texture, 1, 4, false, elem);
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if (!instr.texs.enable_g_component) {
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// Skip the second component
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break;
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}
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}
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offset += 2;
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}
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}
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--shader.scope;
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--shader.scope;
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shader.AddLine("}");
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shader.AddLine("}");
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