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Merge pull request #3807 from ReinUsesLisp/fix-depth-clamp

maxwell_3d: Fix depth clamping register
This commit is contained in:
bunnei 2020-04-30 13:07:31 -04:00 committed by GitHub
commit bf3f030a0d
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 5 additions and 8 deletions

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@ -1179,6 +1179,7 @@ public:
BitField<0, 1, u32> depth_range_0_1; BitField<0, 1, u32> depth_range_0_1;
BitField<3, 1, u32> depth_clamp_near; BitField<3, 1, u32> depth_clamp_near;
BitField<4, 1, u32> depth_clamp_far; BitField<4, 1, u32> depth_clamp_far;
BitField<11, 1, u32> depth_clamp_disabled;
} view_volume_clip_control; } view_volume_clip_control;
INSERT_UNION_PADDING_WORDS(0x1F); INSERT_UNION_PADDING_WORDS(0x1F);

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@ -1022,11 +1022,7 @@ void RasterizerOpenGL::SyncDepthClamp() {
} }
flags[Dirty::DepthClampEnabled] = false; flags[Dirty::DepthClampEnabled] = false;
const auto& state = gpu.regs.view_volume_clip_control; oglEnable(GL_DEPTH_CLAMP, gpu.regs.view_volume_clip_control.depth_clamp_disabled == 0);
UNIMPLEMENTED_IF_MSG(state.depth_clamp_far != state.depth_clamp_near,
"Unimplemented depth clamp separation!");
oglEnable(GL_DEPTH_CLAMP, state.depth_clamp_far || state.depth_clamp_near);
} }
void RasterizerOpenGL::SyncClipEnabled(u32 clip_mask) { void RasterizerOpenGL::SyncClipEnabled(u32 clip_mask) {

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@ -81,7 +81,7 @@ void FixedPipelineState::Rasterizer::Fill(const Maxwell& regs) noexcept {
primitive_restart_enable.Assign(regs.primitive_restart.enabled != 0 ? 1 : 0); primitive_restart_enable.Assign(regs.primitive_restart.enabled != 0 ? 1 : 0);
cull_enable.Assign(regs.cull_test_enabled != 0 ? 1 : 0); cull_enable.Assign(regs.cull_test_enabled != 0 ? 1 : 0);
depth_bias_enable.Assign(enabled_lut[POLYGON_OFFSET_ENABLE_LUT[topology_index]] != 0 ? 1 : 0); depth_bias_enable.Assign(enabled_lut[POLYGON_OFFSET_ENABLE_LUT[topology_index]] != 0 ? 1 : 0);
depth_clamp_enable.Assign(clip.depth_clamp_near == 1 || clip.depth_clamp_far == 1 ? 1 : 0); depth_clamp_disabled.Assign(regs.view_volume_clip_control.depth_clamp_disabled.Value());
ndc_minus_one_to_one.Assign(regs.depth_mode == Maxwell::DepthMode::MinusOneToOne ? 1 : 0); ndc_minus_one_to_one.Assign(regs.depth_mode == Maxwell::DepthMode::MinusOneToOne ? 1 : 0);
cull_face.Assign(PackCullFace(regs.cull_face)); cull_face.Assign(PackCullFace(regs.cull_face));
front_face.Assign(packed_front_face); front_face.Assign(packed_front_face);

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@ -153,7 +153,7 @@ struct FixedPipelineState {
BitField<4, 1, u32> primitive_restart_enable; BitField<4, 1, u32> primitive_restart_enable;
BitField<5, 1, u32> cull_enable; BitField<5, 1, u32> cull_enable;
BitField<6, 1, u32> depth_bias_enable; BitField<6, 1, u32> depth_bias_enable;
BitField<7, 1, u32> depth_clamp_enable; BitField<7, 1, u32> depth_clamp_disabled;
BitField<8, 1, u32> ndc_minus_one_to_one; BitField<8, 1, u32> ndc_minus_one_to_one;
BitField<9, 2, u32> cull_face; BitField<9, 2, u32> cull_face;
BitField<11, 1, u32> front_face; BitField<11, 1, u32> front_face;

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@ -249,7 +249,7 @@ vk::Pipeline VKGraphicsPipeline::CreatePipeline(const RenderPassParams& renderpa
rasterization_ci.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO; rasterization_ci.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO;
rasterization_ci.pNext = nullptr; rasterization_ci.pNext = nullptr;
rasterization_ci.flags = 0; rasterization_ci.flags = 0;
rasterization_ci.depthClampEnable = rs.depth_clamp_enable; rasterization_ci.depthClampEnable = rs.depth_clamp_disabled == 0 ? VK_TRUE : VK_FALSE;
rasterization_ci.rasterizerDiscardEnable = VK_FALSE; rasterization_ci.rasterizerDiscardEnable = VK_FALSE;
rasterization_ci.polygonMode = VK_POLYGON_MODE_FILL; rasterization_ci.polygonMode = VK_POLYGON_MODE_FILL;
rasterization_ci.cullMode = rasterization_ci.cullMode =