Merge pull request #243 from Subv/vertex_buffer
GPU: Added the vertex array registers.
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commit
c286921739
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@ -34,12 +34,14 @@ public:
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struct Regs {
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static constexpr size_t NUM_REGS = 0xE36;
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static constexpr size_t NumVertexArrays = 32;
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static constexpr size_t MaxShaderProgram = 6;
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enum class QueryMode : u32 {
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Write = 0,
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Sync = 1,
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};
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static constexpr size_t MaxShaderProgram = 6;
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enum class ShaderProgram : u32 {
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VertexA = 0,
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VertexB = 1,
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@ -92,7 +94,34 @@ public:
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}
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} query;
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INSERT_PADDING_WORDS(0x13C);
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INSERT_PADDING_WORDS(0x3C);
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struct {
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union {
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BitField<0, 12, u32> stride;
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BitField<12, 1, u32> enable;
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};
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u32 start_high;
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u32 start_low;
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u32 divisor;
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GPUVAddr StartAddress() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(start_high) << 32) |
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start_low);
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}
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} vertex_array[NumVertexArrays];
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INSERT_PADDING_WORDS(0x40);
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struct {
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u32 limit_high;
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u32 limit_low;
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GPUVAddr LimitAddress() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(limit_high) << 32) |
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limit_low);
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}
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} vertex_array_limit[NumVertexArrays];
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struct {
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union {
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@ -148,6 +177,8 @@ private:
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ASSERT_REG_POSITION(code_address, 0x582);
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ASSERT_REG_POSITION(draw, 0x585);
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ASSERT_REG_POSITION(query, 0x6C0);
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ASSERT_REG_POSITION(vertex_array[0], 0x700);
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ASSERT_REG_POSITION(vertex_array_limit[0], 0x7C0);
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ASSERT_REG_POSITION(shader_config[0], 0x800);
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ASSERT_REG_POSITION(shader_code, 0xE24);
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