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GPU: Added register definitions for the vertex buffer base element.

This commit is contained in:
Subv 2018-07-02 11:21:23 -05:00
parent 066d6184d4
commit cc73bad293
1 changed files with 6 additions and 1 deletions
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7
src/video_core/engines/maxwell_3d.h
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@ -455,7 +455,11 @@ public:
u32 enable[NumRenderTargets]; u32 enable[NumRenderTargets];
} blend; } blend;
INSERT_PADDING_WORDS(0x77); INSERT_PADDING_WORDS(0x2D);
u32 vb_element_base;
INSERT_PADDING_WORDS(0x49);
struct { struct {
u32 tsc_address_high; u32 tsc_address_high;
@ -745,6 +749,7 @@ ASSERT_REG_POSITION(vertex_attrib_format[0], 0x458);
ASSERT_REG_POSITION(rt_control, 0x487); ASSERT_REG_POSITION(rt_control, 0x487);
ASSERT_REG_POSITION(independent_blend_enable, 0x4B9); ASSERT_REG_POSITION(independent_blend_enable, 0x4B9);
ASSERT_REG_POSITION(blend, 0x4CF); ASSERT_REG_POSITION(blend, 0x4CF);
ASSERT_REG_POSITION(vb_element_base, 0x50D);
ASSERT_REG_POSITION(tsc, 0x557); ASSERT_REG_POSITION(tsc, 0x557);
ASSERT_REG_POSITION(tic, 0x55D); ASSERT_REG_POSITION(tic, 0x55D);
ASSERT_REG_POSITION(code_address, 0x582); ASSERT_REG_POSITION(code_address, 0x582);