maxwell_3d: implement MME shadow RAM
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e5bb5d13c4
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@ -531,6 +531,13 @@ public:
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Fill = 0x1b02,
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Fill = 0x1b02,
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};
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};
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enum class ShadowRamControl : u32 {
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Track = 0,
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TrackWithFilter = 1,
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Passthrough = 2,
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Replay = 3,
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};
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struct RenderTargetConfig {
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struct RenderTargetConfig {
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u32 address_high;
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u32 address_high;
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u32 address_low;
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u32 address_low;
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@ -674,7 +681,9 @@ public:
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u32 bind;
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u32 bind;
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} macros;
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} macros;
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INSERT_UNION_PADDING_WORDS(0x17);
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ShadowRamControl shadow_ram_control;
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INSERT_UNION_PADDING_WORDS(0x16);
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Upload::Registers upload;
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Upload::Registers upload;
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struct {
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struct {
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@ -1265,6 +1274,9 @@ public:
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};
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};
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} regs{};
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} regs{};
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/// Store temporary hw register values, used by some calls to restore state after a operation
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Regs shadow_state;
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
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static_assert(std::is_trivially_copyable_v<Regs>, "Maxwell3D Regs must be trivially copyable");
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static_assert(std::is_trivially_copyable_v<Regs>, "Maxwell3D Regs must be trivially copyable");
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@ -1458,6 +1470,7 @@ private:
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"Field " #field_name " has invalid position")
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(macros, 0x45);
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ASSERT_REG_POSITION(macros, 0x45);
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ASSERT_REG_POSITION(shadow_ram_control, 0x49);
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ASSERT_REG_POSITION(upload, 0x60);
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ASSERT_REG_POSITION(upload, 0x60);
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ASSERT_REG_POSITION(exec_upload, 0x6C);
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ASSERT_REG_POSITION(exec_upload, 0x6C);
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ASSERT_REG_POSITION(data_upload, 0x6D);
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ASSERT_REG_POSITION(data_upload, 0x6D);
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