Merge pull request #10030 from Wollnashorn/botw-amd-fix
shader_recompiler: Fix ImageGather rounding on AMD/Intel
This commit is contained in:
commit
e0895a8581
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@ -143,6 +143,21 @@ IR::Inst* PrepareSparse(IR::Inst& inst) {
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}
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}
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return sparse_inst;
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return sparse_inst;
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}
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}
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std::string ImageGatherSubpixelOffset(const IR::TextureInstInfo& info, std::string_view texture,
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std::string_view coords) {
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switch (info.type) {
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case TextureType::Color2D:
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case TextureType::Color2DRect:
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return fmt::format("{}+vec2(0.001953125)/vec2(textureSize({}, 0))", coords, texture);
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case TextureType::ColorArray2D:
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case TextureType::ColorCube:
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return fmt::format("vec3({0}.xy+vec2(0.001953125)/vec2(textureSize({1}, 0)),{0}.z)", coords,
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texture);
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default:
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return std::string{coords};
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}
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}
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} // Anonymous namespace
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} // Anonymous namespace
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void EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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void EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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@ -340,6 +355,13 @@ void EmitImageGather(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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LOG_WARNING(Shader_GLSL, "Device does not support sparse texture queries. STUBBING");
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LOG_WARNING(Shader_GLSL, "Device does not support sparse texture queries. STUBBING");
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ctx.AddU1("{}=true;", *sparse_inst);
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ctx.AddU1("{}=true;", *sparse_inst);
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}
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}
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std::string coords_with_subpixel_offset;
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if (ctx.profile.need_gather_subpixel_offset) {
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// Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on
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// AMD hardware as on Maxwell or other Nvidia architectures.
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coords_with_subpixel_offset = ImageGatherSubpixelOffset(info, texture, coords);
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coords = coords_with_subpixel_offset;
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}
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if (!sparse_inst || !supports_sparse) {
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if (!sparse_inst || !supports_sparse) {
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if (offset.IsEmpty()) {
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if (offset.IsEmpty()) {
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ctx.Add("{}=textureGather({},{},int({}));", texel, texture, coords,
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ctx.Add("{}=textureGather({},{},int({}));", texel, texture, coords,
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@ -387,6 +409,13 @@ void EmitImageGatherDref(EmitContext& ctx, IR::Inst& inst, const IR::Value& inde
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LOG_WARNING(Shader_GLSL, "Device does not support sparse texture queries. STUBBING");
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LOG_WARNING(Shader_GLSL, "Device does not support sparse texture queries. STUBBING");
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ctx.AddU1("{}=true;", *sparse_inst);
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ctx.AddU1("{}=true;", *sparse_inst);
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}
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}
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std::string coords_with_subpixel_offset;
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if (ctx.profile.need_gather_subpixel_offset) {
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// Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on
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// AMD hardware as on Maxwell or other Nvidia architectures.
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coords_with_subpixel_offset = ImageGatherSubpixelOffset(info, texture, coords);
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coords = coords_with_subpixel_offset;
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}
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if (!sparse_inst || !supports_sparse) {
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if (!sparse_inst || !supports_sparse) {
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if (offset.IsEmpty()) {
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if (offset.IsEmpty()) {
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ctx.Add("{}=textureGather({},{},{});", texel, texture, coords, dref);
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ctx.Add("{}=textureGather({},{},{});", texel, texture, coords, dref);
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@ -261,6 +261,30 @@ Id BitTest(EmitContext& ctx, Id mask, Id bit) {
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const Id bit_value{ctx.OpBitwiseAnd(ctx.U32[1], shifted, ctx.Const(1u))};
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const Id bit_value{ctx.OpBitwiseAnd(ctx.U32[1], shifted, ctx.Const(1u))};
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return ctx.OpINotEqual(ctx.U1, bit_value, ctx.u32_zero_value);
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return ctx.OpINotEqual(ctx.U1, bit_value, ctx.u32_zero_value);
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}
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}
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Id ImageGatherSubpixelOffset(EmitContext& ctx, const IR::TextureInstInfo& info, Id texture,
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Id coords) {
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// Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on
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// AMD hardware as on Maxwell or other Nvidia architectures.
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const auto calculate_coords{[&](size_t dim) {
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const Id nudge{ctx.Const(0x1p-9f)};
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const Id image_size{ctx.OpImageQuerySizeLod(ctx.U32[dim], texture, ctx.u32_zero_value)};
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Id offset{dim == 2 ? ctx.ConstantComposite(ctx.F32[dim], nudge, nudge)
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: ctx.ConstantComposite(ctx.F32[dim], nudge, nudge, ctx.f32_zero_value)};
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offset = ctx.OpFDiv(ctx.F32[dim], offset, ctx.OpConvertUToF(ctx.F32[dim], image_size));
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return ctx.OpFAdd(ctx.F32[dim], coords, offset);
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}};
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switch (info.type) {
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case TextureType::Color2D:
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case TextureType::Color2DRect:
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return calculate_coords(2);
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case TextureType::ColorArray2D:
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case TextureType::ColorCube:
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return calculate_coords(3);
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default:
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return coords;
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}
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}
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} // Anonymous namespace
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} // Anonymous namespace
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Id EmitBindlessImageSampleImplicitLod(EmitContext&) {
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Id EmitBindlessImageSampleImplicitLod(EmitContext&) {
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@ -423,6 +447,9 @@ Id EmitImageGather(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id
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const IR::Value& offset, const IR::Value& offset2) {
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const IR::Value& offset, const IR::Value& offset2) {
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const auto info{inst->Flags<IR::TextureInstInfo>()};
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const auto info{inst->Flags<IR::TextureInstInfo>()};
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const ImageOperands operands(ctx, offset, offset2);
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const ImageOperands operands(ctx, offset, offset2);
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if (ctx.profile.need_gather_subpixel_offset) {
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coords = ImageGatherSubpixelOffset(ctx, info, TextureImage(ctx, info, index), coords);
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}
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return Emit(&EmitContext::OpImageSparseGather, &EmitContext::OpImageGather, ctx, inst,
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return Emit(&EmitContext::OpImageSparseGather, &EmitContext::OpImageGather, ctx, inst,
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ctx.F32[4], Texture(ctx, info, index), coords, ctx.Const(info.gather_component),
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ctx.F32[4], Texture(ctx, info, index), coords, ctx.Const(info.gather_component),
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operands.MaskOptional(), operands.Span());
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operands.MaskOptional(), operands.Span());
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@ -432,6 +459,9 @@ Id EmitImageGatherDref(EmitContext& ctx, IR::Inst* inst, const IR::Value& index,
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const IR::Value& offset, const IR::Value& offset2, Id dref) {
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const IR::Value& offset, const IR::Value& offset2, Id dref) {
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const auto info{inst->Flags<IR::TextureInstInfo>()};
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const auto info{inst->Flags<IR::TextureInstInfo>()};
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const ImageOperands operands(ctx, offset, offset2);
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const ImageOperands operands(ctx, offset, offset2);
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if (ctx.profile.need_gather_subpixel_offset) {
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coords = ImageGatherSubpixelOffset(ctx, info, TextureImage(ctx, info, index), coords);
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}
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return Emit(&EmitContext::OpImageSparseDrefGather, &EmitContext::OpImageDrefGather, ctx, inst,
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return Emit(&EmitContext::OpImageSparseDrefGather, &EmitContext::OpImageDrefGather, ctx, inst,
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ctx.F32[4], Texture(ctx, info, index), coords, dref, operands.MaskOptional(),
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ctx.F32[4], Texture(ctx, info, index), coords, dref, operands.MaskOptional(),
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operands.Span());
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operands.Span());
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@ -52,6 +52,10 @@ struct Profile {
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bool need_declared_frag_colors{};
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bool need_declared_frag_colors{};
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/// Prevents fast math optimizations that may cause inaccuracies
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/// Prevents fast math optimizations that may cause inaccuracies
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bool need_fastmath_off{};
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bool need_fastmath_off{};
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/// Some GPU vendors use a different rounding precision when calculating texture pixel
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/// coordinates with the 16.8 format in the ImageGather instruction than the Maxwell
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/// architecture. Applying an offset does fix this mismatching rounding behaviour.
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bool need_gather_subpixel_offset{};
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/// OpFClamp is broken and OpFMax + OpFMin should be used instead
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/// OpFClamp is broken and OpFMax + OpFMin should be used instead
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bool has_broken_spirv_clamp{};
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bool has_broken_spirv_clamp{};
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@ -176,6 +176,10 @@ public:
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return vendor_name == "ATI Technologies Inc.";
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return vendor_name == "ATI Technologies Inc.";
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}
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}
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bool IsIntel() const {
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return vendor_name == "Intel";
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}
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bool CanReportMemoryUsage() const {
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bool CanReportMemoryUsage() const {
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return can_report_memory;
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return can_report_memory;
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}
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}
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@ -218,6 +218,7 @@ ShaderCache::ShaderCache(RasterizerOpenGL& rasterizer_, Core::Frontend::EmuWindo
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.lower_left_origin_mode = true,
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.lower_left_origin_mode = true,
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.need_declared_frag_colors = true,
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.need_declared_frag_colors = true,
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.need_fastmath_off = device.NeedsFastmathOff(),
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.need_fastmath_off = device.NeedsFastmathOff(),
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.need_gather_subpixel_offset = device.IsAmd() || device.IsIntel(),
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.has_broken_spirv_clamp = true,
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.has_broken_spirv_clamp = true,
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.has_broken_unsigned_image_offsets = true,
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.has_broken_unsigned_image_offsets = true,
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@ -329,6 +329,11 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, const Device& device
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.lower_left_origin_mode = false,
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.lower_left_origin_mode = false,
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.need_declared_frag_colors = false,
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.need_declared_frag_colors = false,
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.need_gather_subpixel_offset = driver_id == VK_DRIVER_ID_AMD_PROPRIETARY ||
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driver_id == VK_DRIVER_ID_AMD_OPEN_SOURCE ||
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driver_id == VK_DRIVER_ID_MESA_RADV ||
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driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS ||
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driver_id == VK_DRIVER_ID_INTEL_OPEN_SOURCE_MESA,
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.has_broken_spirv_clamp = driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS,
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.has_broken_spirv_clamp = driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS,
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.has_broken_spirv_position_input = driver_id == VK_DRIVER_ID_QUALCOMM_PROPRIETARY,
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.has_broken_spirv_position_input = driver_id == VK_DRIVER_ID_QUALCOMM_PROPRIETARY,
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