Merge pull request #3612 from ReinUsesLisp/red
shader/memory: Implement RED.E.ADD and minor changes to ATOM
This commit is contained in:
commit
e33196d4e7
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@ -1005,6 +1005,12 @@ union Instruction {
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BitField<46, 2, u64> cache_mode;
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} stg;
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union {
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BitField<23, 3, AtomicOp> operation;
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BitField<48, 1, u64> extended;
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BitField<20, 3, GlobalAtomicType> type;
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} red;
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union {
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BitField<52, 4, AtomicOp> operation;
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BitField<49, 3, GlobalAtomicType> type;
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@ -1787,6 +1793,7 @@ public:
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ST_S,
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ST, // Store in generic memory
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STG, // Store in global memory
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RED, // Reduction operation
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ATOM, // Atomic operation on global memory
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ATOMS, // Atomic operation on shared memory
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AL2P, // Transforms attribute memory into physical memory
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@ -2097,6 +2104,7 @@ private:
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INST("1110111101010---", Id::ST_L, Type::Memory, "ST_L"),
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INST("101-------------", Id::ST, Type::Memory, "ST"),
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INST("1110111011011---", Id::STG, Type::Memory, "STG"),
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INST("1110101111111---", Id::RED, Type::Memory, "RED"),
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INST("11101101--------", Id::ATOM, Type::Memory, "ATOM"),
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INST("11101100--------", Id::ATOMS, Type::Memory, "ATOMS"),
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INST("1110111110100---", Id::AL2P, Type::Memory, "AL2P"),
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@ -2119,8 +2119,14 @@ private:
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return {};
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}
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return {fmt::format("atomic{}({}, {})", opname, Visit(operation[0]).GetCode(),
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Visit(operation[1]).As(type)),
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type};
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Visit(operation[1]).AsUint()),
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Type::Uint};
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}
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template <const std::string_view& opname, Type type>
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Expression Reduce(Operation operation) {
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code.AddLine("{};", Atomic<opname, type>(operation).GetCode());
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return {};
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}
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Expression Branch(Operation operation) {
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@ -2479,6 +2485,20 @@ private:
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&GLSLDecompiler::Atomic<Func::Or, Type::Int>,
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&GLSLDecompiler::Atomic<Func::Xor, Type::Int>,
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&GLSLDecompiler::Reduce<Func::Add, Type::Uint>,
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&GLSLDecompiler::Reduce<Func::Min, Type::Uint>,
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&GLSLDecompiler::Reduce<Func::Max, Type::Uint>,
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&GLSLDecompiler::Reduce<Func::And, Type::Uint>,
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&GLSLDecompiler::Reduce<Func::Or, Type::Uint>,
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&GLSLDecompiler::Reduce<Func::Xor, Type::Uint>,
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&GLSLDecompiler::Reduce<Func::Add, Type::Int>,
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&GLSLDecompiler::Reduce<Func::Min, Type::Int>,
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&GLSLDecompiler::Reduce<Func::Max, Type::Int>,
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&GLSLDecompiler::Reduce<Func::And, Type::Int>,
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&GLSLDecompiler::Reduce<Func::Or, Type::Int>,
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&GLSLDecompiler::Reduce<Func::Xor, Type::Int>,
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&GLSLDecompiler::Branch,
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&GLSLDecompiler::BranchIndirect,
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&GLSLDecompiler::PushFlowStack,
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@ -1938,11 +1938,8 @@ private:
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return {};
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}
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template <Id (Module::*func)(Id, Id, Id, Id, Id), Type result_type,
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Type value_type = result_type>
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template <Id (Module::*func)(Id, Id, Id, Id, Id)>
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Expression Atomic(Operation operation) {
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const Id type_def = GetTypeDefinition(result_type);
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Id pointer;
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if (const auto smem = std::get_if<SmemNode>(&*operation[0])) {
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pointer = GetSharedMemoryPointer(*smem);
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@ -1950,15 +1947,19 @@ private:
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pointer = GetGlobalMemoryPointer(*gmem);
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} else {
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UNREACHABLE();
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return {Constant(type_def, 0), result_type};
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return {v_float_zero, Type::Float};
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}
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const Id value = As(Visit(operation[1]), value_type);
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const Id scope = Constant(t_uint, static_cast<u32>(spv::Scope::Device));
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const Id semantics = Constant(type_def, 0);
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const Id semantics = Constant(t_uint, 0);
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const Id value = AsUint(Visit(operation[1]));
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return {(this->*func)(type_def, pointer, scope, semantics, value), result_type};
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return {(this->*func)(t_uint, pointer, scope, semantics, value), Type::Uint};
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}
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template <Id (Module::*func)(Id, Id, Id, Id, Id)>
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Expression Reduce(Operation operation) {
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Atomic<func>(operation);
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return {};
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}
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Expression Branch(Operation operation) {
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@ -2547,21 +2548,35 @@ private:
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&SPIRVDecompiler::AtomicImageXor,
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&SPIRVDecompiler::AtomicImageExchange,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicExchange, Type::Uint>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicIAdd, Type::Uint>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicUMin, Type::Uint>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicUMax, Type::Uint>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicAnd, Type::Uint>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicOr, Type::Uint>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicXor, Type::Uint>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicExchange>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicIAdd>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicUMin>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicUMax>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicAnd>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicOr>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicXor>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicExchange, Type::Int>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicIAdd, Type::Int>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicSMin, Type::Int>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicSMax, Type::Int>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicAnd, Type::Int>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicOr, Type::Int>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicXor, Type::Int>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicExchange>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicIAdd>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicSMin>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicSMax>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicAnd>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicOr>,
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&SPIRVDecompiler::Atomic<&Module::OpAtomicXor>,
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&SPIRVDecompiler::Reduce<&Module::OpAtomicIAdd>,
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&SPIRVDecompiler::Reduce<&Module::OpAtomicUMin>,
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&SPIRVDecompiler::Reduce<&Module::OpAtomicUMax>,
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&SPIRVDecompiler::Reduce<&Module::OpAtomicAnd>,
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&SPIRVDecompiler::Reduce<&Module::OpAtomicOr>,
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&SPIRVDecompiler::Reduce<&Module::OpAtomicXor>,
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&SPIRVDecompiler::Reduce<&Module::OpAtomicIAdd>,
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&SPIRVDecompiler::Reduce<&Module::OpAtomicSMin>,
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&SPIRVDecompiler::Reduce<&Module::OpAtomicSMax>,
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&SPIRVDecompiler::Reduce<&Module::OpAtomicAnd>,
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&SPIRVDecompiler::Reduce<&Module::OpAtomicOr>,
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&SPIRVDecompiler::Reduce<&Module::OpAtomicXor>,
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&SPIRVDecompiler::Branch,
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&SPIRVDecompiler::BranchIndirect,
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@ -3,7 +3,9 @@
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <utility>
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#include <vector>
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#include <fmt/format.h>
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#include "common/alignment.h"
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@ -16,6 +18,7 @@
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namespace VideoCommon::Shader {
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using std::move;
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using Tegra::Shader::AtomicOp;
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using Tegra::Shader::AtomicType;
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using Tegra::Shader::Attribute;
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@ -27,29 +30,26 @@ using Tegra::Shader::StoreType;
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namespace {
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Node GetAtomOperation(AtomicOp op, bool is_signed, Node memory, Node data) {
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const OperationCode operation_code = [op] {
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switch (op) {
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case AtomicOp::Add:
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return OperationCode::AtomicIAdd;
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case AtomicOp::Min:
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return OperationCode::AtomicIMin;
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case AtomicOp::Max:
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return OperationCode::AtomicIMax;
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case AtomicOp::And:
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return OperationCode::AtomicIAnd;
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case AtomicOp::Or:
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return OperationCode::AtomicIOr;
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case AtomicOp::Xor:
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return OperationCode::AtomicIXor;
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case AtomicOp::Exch:
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return OperationCode::AtomicIExchange;
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default:
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UNIMPLEMENTED_MSG("op={}", static_cast<int>(op));
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return OperationCode::AtomicIAdd;
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}
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}();
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return SignedOperation(operation_code, is_signed, std::move(memory), std::move(data));
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OperationCode GetAtomOperation(AtomicOp op) {
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switch (op) {
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case AtomicOp::Add:
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return OperationCode::AtomicIAdd;
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case AtomicOp::Min:
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return OperationCode::AtomicIMin;
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case AtomicOp::Max:
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return OperationCode::AtomicIMax;
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case AtomicOp::And:
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return OperationCode::AtomicIAnd;
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case AtomicOp::Or:
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return OperationCode::AtomicIOr;
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case AtomicOp::Xor:
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return OperationCode::AtomicIXor;
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case AtomicOp::Exch:
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return OperationCode::AtomicIExchange;
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default:
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UNIMPLEMENTED_MSG("op={}", static_cast<int>(op));
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return OperationCode::AtomicIAdd;
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}
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}
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bool IsUnaligned(Tegra::Shader::UniformType uniform_type) {
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@ -90,23 +90,22 @@ u32 GetMemorySize(Tegra::Shader::UniformType uniform_type) {
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Node ExtractUnaligned(Node value, Node address, u32 mask, u32 size) {
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Node offset = Operation(OperationCode::UBitwiseAnd, address, Immediate(mask));
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offset = Operation(OperationCode::ULogicalShiftLeft, std::move(offset), Immediate(3));
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return Operation(OperationCode::UBitfieldExtract, std::move(value), std::move(offset),
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Immediate(size));
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offset = Operation(OperationCode::ULogicalShiftLeft, move(offset), Immediate(3));
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return Operation(OperationCode::UBitfieldExtract, move(value), move(offset), Immediate(size));
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}
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Node InsertUnaligned(Node dest, Node value, Node address, u32 mask, u32 size) {
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Node offset = Operation(OperationCode::UBitwiseAnd, std::move(address), Immediate(mask));
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offset = Operation(OperationCode::ULogicalShiftLeft, std::move(offset), Immediate(3));
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return Operation(OperationCode::UBitfieldInsert, std::move(dest), std::move(value),
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std::move(offset), Immediate(size));
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Node offset = Operation(OperationCode::UBitwiseAnd, move(address), Immediate(mask));
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offset = Operation(OperationCode::ULogicalShiftLeft, move(offset), Immediate(3));
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return Operation(OperationCode::UBitfieldInsert, move(dest), move(value), move(offset),
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Immediate(size));
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}
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Node Sign16Extend(Node value) {
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Node sign = Operation(OperationCode::UBitwiseAnd, value, Immediate(1U << 15));
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Node is_sign = Operation(OperationCode::LogicalUEqual, std::move(sign), Immediate(1U << 15));
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Node is_sign = Operation(OperationCode::LogicalUEqual, move(sign), Immediate(1U << 15));
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Node extend = Operation(OperationCode::Select, is_sign, Immediate(0xFFFF0000), Immediate(0));
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return Operation(OperationCode::UBitwiseOr, std::move(value), std::move(extend));
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return Operation(OperationCode::UBitwiseOr, move(value), move(extend));
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}
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} // Anonymous namespace
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@ -379,20 +378,36 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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if (IsUnaligned(type)) {
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const u32 mask = GetUnalignedMask(type);
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value = InsertUnaligned(gmem, std::move(value), real_address, mask, size);
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value = InsertUnaligned(gmem, move(value), real_address, mask, size);
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}
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bb.push_back(Operation(OperationCode::Assign, gmem, value));
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}
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break;
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}
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case OpCode::Id::RED: {
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UNIMPLEMENTED_IF_MSG(instr.red.type != GlobalAtomicType::U32);
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UNIMPLEMENTED_IF_MSG(instr.red.operation != AtomicOp::Add);
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const auto [real_address, base_address, descriptor] =
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TrackGlobalMemory(bb, instr, true, true);
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if (!real_address || !base_address) {
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// Tracking failed, skip atomic.
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break;
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}
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Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor);
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Node value = GetRegister(instr.gpr0);
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bb.push_back(Operation(OperationCode::ReduceIAdd, move(gmem), move(value)));
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break;
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}
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case OpCode::Id::ATOM: {
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UNIMPLEMENTED_IF_MSG(instr.atom.operation == AtomicOp::Inc ||
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instr.atom.operation == AtomicOp::Dec ||
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instr.atom.operation == AtomicOp::SafeAdd,
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"operation={}", static_cast<int>(instr.atom.operation.Value()));
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UNIMPLEMENTED_IF_MSG(instr.atom.type == GlobalAtomicType::S64 ||
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instr.atom.type == GlobalAtomicType::U64,
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instr.atom.type == GlobalAtomicType::U64 ||
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instr.atom.type == GlobalAtomicType::F16x2_FTZ_RN ||
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instr.atom.type == GlobalAtomicType::F32_FTZ_RN,
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"type={}", static_cast<int>(instr.atom.type.Value()));
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const auto [real_address, base_address, descriptor] =
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@ -403,11 +418,11 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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}
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const bool is_signed =
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instr.atoms.type == AtomicType::S32 || instr.atoms.type == AtomicType::S64;
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instr.atom.type == GlobalAtomicType::S32 || instr.atom.type == GlobalAtomicType::S64;
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Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor);
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Node value = GetAtomOperation(static_cast<AtomicOp>(instr.atom.operation), is_signed, gmem,
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GetRegister(instr.gpr20));
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SetRegister(bb, instr.gpr0, std::move(value));
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SetRegister(bb, instr.gpr0,
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SignedOperation(GetAtomOperation(instr.atom.operation), is_signed, gmem,
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GetRegister(instr.gpr20)));
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break;
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}
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case OpCode::Id::ATOMS: {
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@ -421,11 +436,10 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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instr.atoms.type == AtomicType::S32 || instr.atoms.type == AtomicType::S64;
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const s32 offset = instr.atoms.GetImmediateOffset();
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Node address = GetRegister(instr.gpr8);
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address = Operation(OperationCode::IAdd, std::move(address), Immediate(offset));
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Node value =
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GetAtomOperation(static_cast<AtomicOp>(instr.atoms.operation), is_signed,
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GetSharedMemory(std::move(address)), GetRegister(instr.gpr20));
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SetRegister(bb, instr.gpr0, std::move(value));
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address = Operation(OperationCode::IAdd, move(address), Immediate(offset));
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SetRegister(bb, instr.gpr0,
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SignedOperation(GetAtomOperation(instr.atoms.operation), is_signed,
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GetSharedMemory(move(address)), GetRegister(instr.gpr20)));
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break;
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}
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case OpCode::Id::AL2P: {
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@ -178,6 +178,20 @@ enum class OperationCode {
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AtomicIOr, /// (memory, int) -> int
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AtomicIXor, /// (memory, int) -> int
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ReduceUAdd, /// (memory, uint) -> void
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ReduceUMin, /// (memory, uint) -> void
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ReduceUMax, /// (memory, uint) -> void
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ReduceUAnd, /// (memory, uint) -> void
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ReduceUOr, /// (memory, uint) -> void
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ReduceUXor, /// (memory, uint) -> void
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ReduceIAdd, /// (memory, int) -> void
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ReduceIMin, /// (memory, int) -> void
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ReduceIMax, /// (memory, int) -> void
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ReduceIAnd, /// (memory, int) -> void
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ReduceIOr, /// (memory, int) -> void
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ReduceIXor, /// (memory, int) -> void
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Branch, /// (uint branch_target) -> void
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BranchIndirect, /// (uint branch_target) -> void
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PushFlowStack, /// (uint branch_target) -> void
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