Merge pull request #514 from Subv/lop32i
GPU: Implemented the LOP32I instruction.
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commit
e8bfff7b4b
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@ -156,6 +156,13 @@ enum class PredOperation : u64 {
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Xor = 2,
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};
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enum class LogicOperation : u64 {
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And = 0,
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Or = 1,
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Xor = 2,
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PassB = 3,
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};
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enum class SubOp : u64 {
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Cos = 0x0,
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Sin = 0x1,
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@ -202,6 +209,12 @@ union Instruction {
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BitField<42, 1, u64> negate_pred;
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} fmnmx;
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union {
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BitField<53, 2, LogicOperation> operation;
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BitField<55, 1, u64> invert_a;
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BitField<56, 1, u64> invert_b;
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} lop;
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float GetImm20_19() const {
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float result{};
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u32 imm{static_cast<u32>(imm20_19)};
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@ -391,6 +404,7 @@ public:
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enum class Type {
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Trivial,
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Arithmetic,
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Logic,
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Ffma,
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Flow,
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Memory,
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@ -524,7 +538,6 @@ private:
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INST("0100110010110---", Id::F2I_C, Type::Arithmetic, "F2I_C"),
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INST("0101110010110---", Id::F2I_R, Type::Arithmetic, "F2I_R"),
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INST("0011100-10110---", Id::F2I_IMM, Type::Arithmetic, "F2I_IMM"),
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INST("000001----------", Id::LOP32I, Type::Arithmetic, "LOP32I"),
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INST("0100110010011---", Id::MOV_C, Type::Arithmetic, "MOV_C"),
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INST("0101110010011---", Id::MOV_R, Type::Arithmetic, "MOV_R"),
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INST("0011100-10011---", Id::MOV_IMM, Type::Arithmetic, "MOV_IMM"),
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@ -535,6 +548,7 @@ private:
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INST("0100110001100---", Id::FMNMX_C, Type::Arithmetic, "FMNMX_C"),
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INST("0101110001100---", Id::FMNMX_R, Type::Arithmetic, "FMNMX_R"),
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INST("0011100-01100---", Id::FMNMX_IMM, Type::Arithmetic, "FMNMX_IMM"),
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INST("000001----------", Id::LOP32I, Type::Logic, "LOP32I"),
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INST("0100110011100---", Id::I2I_C, Type::Conversion, "I2I_C"),
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INST("0101110011100---", Id::I2I_R, Type::Conversion, "I2I_R"),
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INST("01110001-1000---", Id::I2I_IMM, Type::Conversion, "I2I_IMM"),
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@ -841,6 +841,49 @@ private:
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}
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break;
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}
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case OpCode::Type::Logic: {
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std::string op_a = regs.GetRegisterAsInteger(instr.gpr8, 0, false);
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if (instr.alu.lop.invert_a)
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op_a = "~(" + op_a + ')';
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switch (opcode->GetId()) {
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case OpCode::Id::LOP32I: {
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u32 imm = static_cast<u32>(instr.alu.imm20_32.Value());
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if (instr.alu.lop.invert_b)
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imm = ~imm;
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switch (instr.alu.lop.operation) {
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case Tegra::Shader::LogicOperation::And: {
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regs.SetRegisterToInteger(instr.gpr0, false, 0,
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'(' + op_a + " & " + std::to_string(imm) + ')', 1, 1);
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break;
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}
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case Tegra::Shader::LogicOperation::Or: {
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regs.SetRegisterToInteger(instr.gpr0, false, 0,
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'(' + op_a + " | " + std::to_string(imm) + ')', 1, 1);
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break;
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}
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case Tegra::Shader::LogicOperation::Xor: {
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regs.SetRegisterToInteger(instr.gpr0, false, 0,
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'(' + op_a + " ^ " + std::to_string(imm) + ')', 1, 1);
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break;
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}
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default:
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NGLOG_CRITICAL(HW_GPU, "Unimplemented lop32i operation: {}",
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static_cast<u32>(instr.alu.lop.operation.Value()));
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UNREACHABLE();
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}
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break;
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}
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default: {
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NGLOG_CRITICAL(HW_GPU, "Unhandled logic instruction: {}", opcode->GetName());
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UNREACHABLE();
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}
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}
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break;
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}
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case OpCode::Type::Ffma: {
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std::string op_a = regs.GetRegisterAsFloat(instr.gpr8);
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std::string op_b = instr.ffma.negate_b ? "-" : "";
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