Merge pull request #258 from Subv/gpu_attribs
GPU: Added vertex attrib format and triangle topology registers
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commit
ec5ede68e7
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@ -34,6 +34,7 @@ public:
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static constexpr size_t NumRenderTargets = 8;
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static constexpr size_t NumCBData = 16;
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static constexpr size_t NumVertexArrays = 32;
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static constexpr size_t NumVertexAttributes = 32;
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static constexpr size_t MaxShaderProgram = 6;
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static constexpr size_t MaxShaderStage = 5;
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// Maximum number of const buffers per shader stage.
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@ -83,7 +84,14 @@ public:
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}
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} rt[NumRenderTargets];
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INSERT_PADDING_WORDS(0x178);
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INSERT_PADDING_WORDS(0xDD);
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struct {
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u32 first;
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u32 count;
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} vertex_buffer;
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INSERT_PADDING_WORDS(0x99);
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struct {
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u32 address_high;
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@ -98,7 +106,18 @@ public:
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}
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} zeta;
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INSERT_PADDING_WORDS(0x8A);
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INSERT_PADDING_WORDS(0x5B);
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union {
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BitField<0, 5, u32> buffer;
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BitField<6, 1, u32> constant;
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BitField<7, 14, u32> offset;
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BitField<21, 6, u32> size;
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BitField<27, 3, u32> type;
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BitField<31, 1, u32> bgra;
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} vertex_attrib_format[NumVertexAttributes];
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INSERT_PADDING_WORDS(0xF);
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struct {
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union {
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@ -146,7 +165,10 @@ public:
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INSERT_PADDING_WORDS(1);
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struct {
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u32 vertex_end_gl;
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u32 vertex_begin_gl;
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union {
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u32 vertex_begin_gl;
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BitField<0, 16, u32> topology;
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};
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} draw;
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INSERT_PADDING_WORDS(0x139);
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struct {
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@ -336,7 +358,9 @@ private:
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(rt, 0x200);
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ASSERT_REG_POSITION(vertex_buffer, 0x35D);
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ASSERT_REG_POSITION(zeta, 0x3F8);
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ASSERT_REG_POSITION(vertex_attrib_format[0], 0x458);
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ASSERT_REG_POSITION(rt_control, 0x487);
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ASSERT_REG_POSITION(tsc, 0x557);
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ASSERT_REG_POSITION(tic, 0x55D);
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