dyncom: Get rid of skyeye typedefs
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0191c26521
commit
4bb1a5ca47
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@ -219,7 +219,7 @@ void DisassemblerWidget::OnToggleStartStop() {
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}
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void DisassemblerWidget::OnDebugModeEntered() {
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ARMword next_instr = Core::g_app_core->GetPC();
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u32 next_instr = Core::g_app_core->GetPC();
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if (model->GetBreakPoints().IsAddressBreakPoint(next_instr))
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emu_thread->SetRunning(false);
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@ -51,22 +51,21 @@ typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper);
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// Defines a reservation granule of 2 words, which protects the first 2 words starting at the tag.
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// This is the smallest granule allowed by the v7 spec, and is coincidentally just large enough to
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// support LDR/STREXD.
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static const ARMword RESERVATION_GRANULE_MASK = 0xFFFFFFF8;
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static const u32 RESERVATION_GRANULE_MASK = 0xFFFFFFF8;
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// Exclusive memory access
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static int exclusive_detect(ARMul_State* state, ARMword addr) {
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static int exclusive_detect(ARMul_State* state, u32 addr) {
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if(state->exclusive_tag == (addr & RESERVATION_GRANULE_MASK))
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return 0;
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else
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return -1;
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}
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static void add_exclusive_addr(ARMul_State* state, ARMword addr){
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static void add_exclusive_addr(ARMul_State* state, u32 addr){
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state->exclusive_tag = addr & RESERVATION_GRANULE_MASK;
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return;
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}
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static void remove_exclusive(ARMul_State* state, ARMword addr){
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static void remove_exclusive(ARMul_State* state, u32 addr){
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state->exclusive_tag = 0xFFFFFFFF;
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}
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@ -14,7 +14,7 @@
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tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
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tdstate valid = t_uninitialized;
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ARMword tinstr = instr;
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u32 tinstr = instr;
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// The endian should be judge here
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if((addr & 0x3) != 0)
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@ -37,7 +37,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
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case 3: // ADD/SUB
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{
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static const ARMword subset[4] = {
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static const u32 subset[4] = {
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0xE0900000, // ADDS Rd,Rs,Rn
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0xE0500000, // SUBS Rd,Rs,Rn
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0xE2900000, // ADDS Rd,Rs,#imm3
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@ -56,7 +56,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
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case 6: // ADD
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case 7: // SUB
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{
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static const ARMword subset[4] = {
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static const u32 subset[4] = {
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0xE3B00000, // MOVS Rd,#imm8
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0xE3500000, // CMP Rd,#imm8
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0xE2900000, // ADDS Rd,Rd,#imm8
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@ -85,7 +85,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
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};
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static const struct {
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ARMword opcode;
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u32 opcode;
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otype type;
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} subset[16] = {
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{ 0xE0100000, t_norm }, // ANDS Rd,Rd,Rs
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@ -130,8 +130,8 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
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break;
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}
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} else {
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ARMword Rd = ((tinstr & 0x0007) >> 0);
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ARMword Rs = ((tinstr & 0x0078) >> 3);
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u32 Rd = ((tinstr & 0x0007) >> 0);
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u32 Rs = ((tinstr & 0x0078) >> 3);
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if (tinstr & (1 << 7))
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Rd += 8;
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@ -185,7 +185,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
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case 10:
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case 11:
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{
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static const ARMword subset[8] = {
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static const u32 subset[8] = {
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0xE7800000, // STR Rd,[Rb,Ro]
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0xE18000B0, // STRH Rd,[Rb,Ro]
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0xE7C00000, // STRB Rd,[Rb,Ro]
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@ -208,7 +208,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
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case 14: // STRB Rd,[Rb,#imm5]
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case 15: // LDRB Rd,[Rb,#imm5]
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{
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static const ARMword subset[4] = {
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static const u32 subset[4] = {
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0xE5800000, // STR Rd,[Rb,#imm5]
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0xE5900000, // LDR Rd,[Rb,#imm5]
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0xE5C00000, // STRB Rd,[Rb,#imm5]
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@ -275,7 +275,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
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| BITS(tinstr, 0, 3) // imm4 field;
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| (BITS(tinstr, 4, 7) << 8); // beginning 4 bits of imm12
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} else if ((tinstr & 0x0F00) == 0x0200) {
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static const ARMword subset[4] = {
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static const u32 subset[4] = {
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0xE6BF0070, // SXTH
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0xE6AF0070, // SXTB
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0xE6FF0070, // UXTH
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@ -299,7 +299,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
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| (BIT(tinstr, 4) << 18); // enable bit
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}
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} else if ((tinstr & 0x0F00) == 0x0a00) {
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static const ARMword subset[3] = {
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static const u32 subset[3] = {
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0xE6BF0F30, // REV
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0xE6BF0FB0, // REV16
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0xE6FF0FB0, // REVSH
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@ -309,7 +309,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
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| (BITS(tinstr, 0, 2) << 12) // Rd
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| BITS(tinstr, 3, 5); // Rm
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} else {
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static const ARMword subset[4] = {
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static const u32 subset[4] = {
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0xE92D0000, // STMDB sp!,{rlist}
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0xE92D4000, // STMDB sp!,{rlist,lr}
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0xE8BD0000, // LDMIA sp!,{rlist}
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@ -44,50 +44,45 @@ enum {
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ABORT_BASE_UPDATED = 2
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};
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typedef u64 ARMdword; // must be 64 bits wide
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typedef u32 ARMword; // must be 32 bits wide
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typedef u16 ARMhword; // must be 16 bits wide
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typedef u8 ARMbyte; // must be 8 bits wide
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#define VFP_REG_NUM 64
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struct ARMul_State
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{
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ARMword Emulate; // To start and stop emulation
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u32 Emulate; // To start and stop emulation
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// Order of the following register should not be modified
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ARMword Reg[16]; // The current register file
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ARMword Cpsr; // The current PSR
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ARMword Spsr_copy;
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ARMword phys_pc;
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ARMword Reg_usr[2];
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ARMword Reg_svc[2]; // R13_SVC R14_SVC
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ARMword Reg_abort[2]; // R13_ABORT R14_ABORT
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ARMword Reg_undef[2]; // R13 UNDEF R14 UNDEF
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ARMword Reg_irq[2]; // R13_IRQ R14_IRQ
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ARMword Reg_firq[7]; // R8---R14 FIRQ
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ARMword Spsr[7]; // The exception psr's
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ARMword Mode; // The current mode
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ARMword Bank; // The current register bank
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ARMword exclusive_tag; // The address for which the local monitor is in exclusive access mode
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ARMword exclusive_state;
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ARMword exclusive_result;
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ARMword CP15[CP15_REGISTER_COUNT];
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u32 Reg[16]; // The current register file
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u32 Cpsr; // The current PSR
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u32 Spsr_copy;
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u32 phys_pc;
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u32 Reg_usr[2];
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u32 Reg_svc[2]; // R13_SVC R14_SVC
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u32 Reg_abort[2]; // R13_ABORT R14_ABORT
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u32 Reg_undef[2]; // R13 UNDEF R14 UNDEF
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u32 Reg_irq[2]; // R13_IRQ R14_IRQ
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u32 Reg_firq[7]; // R8---R14 FIRQ
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u32 Spsr[7]; // The exception psr's
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u32 Mode; // The current mode
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u32 Bank; // The current register bank
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u32 exclusive_tag; // The address for which the local monitor is in exclusive access mode
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u32 exclusive_state;
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u32 exclusive_result;
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u32 CP15[CP15_REGISTER_COUNT];
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// FPSID, FPSCR, and FPEXC
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ARMword VFP[VFP_SYSTEM_REGISTER_COUNT];
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u32 VFP[VFP_SYSTEM_REGISTER_COUNT];
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// VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
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// VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),
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// and only 32 singleword registers are accessible (S0-S31).
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ARMword ExtReg[VFP_REG_NUM];
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u32 ExtReg[VFP_REG_NUM];
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/* ---- End of the ordered registers ---- */
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ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed
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u32 NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed
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unsigned int shifter_carry_out;
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// Add armv6 flags dyf:2010-08-09
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ARMword GEFlag, EFlag, AFlag, QFlag;
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u32 GEFlag, EFlag, AFlag, QFlag;
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ARMword TFlag; // Thumb state
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u32 TFlag; // Thumb state
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unsigned long long NumInstrs; // The number of instructions executed
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unsigned NumInstrsToExecute;
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@ -43,7 +43,7 @@ void VFPInit(ARMul_State* state)
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state->VFP[VFP_MVFR1] = 0;
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}
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void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value)
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void VMOVBRS(ARMul_State* state, u32 to_arm, u32 t, u32 n, u32* value)
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{
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if (to_arm)
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{
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@ -55,7 +55,7 @@ void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword*
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}
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}
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void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2)
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void VMOVBRRD(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2)
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{
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if (to_arm)
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{
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@ -68,7 +68,7 @@ void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword
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state->ExtReg[n*2] = *value1;
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}
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}
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void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2)
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void VMOVBRRSS(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2)
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{
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if (to_arm)
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{
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@ -82,7 +82,7 @@ void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMwor
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}
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}
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void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm)
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void VMOVI(ARMul_State* state, u32 single, u32 d, u32 imm)
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{
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if (single)
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{
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@ -95,7 +95,7 @@ void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm)
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state->ExtReg[d*2] = 0;
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}
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}
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void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword m)
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void VMOVR(ARMul_State* state, u32 single, u32 d, u32 m)
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{
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if (single)
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{
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@ -36,8 +36,8 @@ void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpsc
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u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
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u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
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void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value);
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void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2);
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void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2);
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void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm);
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void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword imm);
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void VMOVBRS(ARMul_State* state, u32 to_arm, u32 t, u32 n, u32* value);
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void VMOVBRRD(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2);
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void VMOVBRRSS(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2);
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void VMOVI(ARMul_State* state, u32 single, u32 d, u32 imm);
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void VMOVR(ARMul_State* state, u32 single, u32 d, u32 imm);
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@ -415,7 +415,7 @@ struct op {
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u32 flags;
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};
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static inline u32 fls(ARMword x)
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static inline u32 fls(u32 x)
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{
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int r = 32;
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@ -70,9 +70,9 @@ static void vfp_double_dump(const char *str, struct vfp_double *d)
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static void vfp_double_normalise_denormal(struct vfp_double *vd)
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{
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int bits = 31 - fls((ARMword)(vd->significand >> 32));
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int bits = 31 - fls((u32)(vd->significand >> 32));
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if (bits == 31)
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bits = 63 - fls((ARMword)vd->significand);
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bits = 63 - fls((u32)vd->significand);
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vfp_double_dump("normalise_denormal: in", vd);
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@ -109,9 +109,9 @@ u32 vfp_double_normaliseround(ARMul_State* state, int dd, struct vfp_double *vd,
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exponent = vd->exponent;
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significand = vd->significand;
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shift = 32 - fls((ARMword)(significand >> 32));
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shift = 32 - fls((u32)(significand >> 32));
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if (shift == 32)
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shift = 64 - fls((ARMword)significand);
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shift = 64 - fls((u32)significand);
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if (shift) {
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exponent -= shift;
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significand <<= shift;
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@ -566,7 +566,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
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/*
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* 2^0 <= m < 2^32-2^8
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*/
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d = (ARMword)((vdm.significand << 1) >> shift);
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d = (u32)((vdm.significand << 1) >> shift);
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rem = vdm.significand << (65 - shift);
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if (rmode == FPSCR_ROUND_NEAREST) {
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@ -647,7 +647,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
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int shift = 1023 + 63 - vdm.exponent; /* 58 */
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u64 rem, incr = 0;
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d = (ARMword)((vdm.significand << 1) >> shift);
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d = (u32)((vdm.significand << 1) >> shift);
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rem = vdm.significand << (65 - shift);
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if (rmode == FPSCR_ROUND_NEAREST) {
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