Merge pull request #1290 from FernandoS27/shader-header
Implemented (Partialy) Shader Header
This commit is contained in:
commit
fafc80d72e
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@ -14,6 +14,7 @@ add_library(video_core STATIC
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engines/maxwell_dma.cpp
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engines/maxwell_dma.h
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engines/shader_bytecode.h
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engines/shader_header.h
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gpu.cpp
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gpu.h
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macro_interpreter.cpp
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@ -0,0 +1,103 @@
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// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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namespace Tegra::Shader {
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enum class OutputTopology : u32 {
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PointList = 1,
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LineStrip = 6,
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TriangleStrip = 7,
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};
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// Documentation in:
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// http://download.nvidia.com/open-gpu-doc/Shader-Program-Header/1/Shader-Program-Header.html#ImapTexture
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struct Header {
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union {
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BitField<0, 5, u32> sph_type;
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BitField<5, 5, u32> version;
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BitField<10, 4, u32> shader_type;
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BitField<14, 1, u32> mrt_enable;
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BitField<15, 1, u32> kills_pixels;
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BitField<16, 1, u32> does_global_store;
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BitField<17, 4, u32> sass_version;
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BitField<21, 5, u32> reserved;
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BitField<26, 1, u32> does_load_or_store;
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BitField<27, 1, u32> does_fp64;
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BitField<28, 4, u32> stream_out_mask;
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} common0;
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union {
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BitField<0, 24, u32> shader_local_memory_low_size;
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BitField<24, 8, u32> per_patch_attribute_count;
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} common1;
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union {
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BitField<0, 24, u32> shader_local_memory_high_size;
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BitField<24, 8, u32> threads_per_input_primitive;
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} common2;
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union {
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BitField<0, 24, u32> shader_local_memory_crs_size;
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BitField<24, 4, OutputTopology> output_topology;
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BitField<28, 4, u32> reserved;
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} common3;
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union {
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BitField<0, 12, u32> max_output_vertices;
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BitField<12, 8, u32> store_req_start; // NOTE: not used by geometry shaders.
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BitField<24, 4, u32> reserved;
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BitField<12, 8, u32> store_req_end; // NOTE: not used by geometry shaders.
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} common4;
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union {
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struct {
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INSERT_PADDING_BYTES(3); // ImapSystemValuesA
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INSERT_PADDING_BYTES(1); // ImapSystemValuesB
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INSERT_PADDING_BYTES(16); // ImapGenericVector[32]
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INSERT_PADDING_BYTES(2); // ImapColor
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INSERT_PADDING_BYTES(2); // ImapSystemValuesC
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INSERT_PADDING_BYTES(5); // ImapFixedFncTexture[10]
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INSERT_PADDING_BYTES(1); // ImapReserved
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INSERT_PADDING_BYTES(3); // OmapSystemValuesA
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INSERT_PADDING_BYTES(1); // OmapSystemValuesB
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INSERT_PADDING_BYTES(16); // OmapGenericVector[32]
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INSERT_PADDING_BYTES(2); // OmapColor
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INSERT_PADDING_BYTES(2); // OmapSystemValuesC
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INSERT_PADDING_BYTES(5); // OmapFixedFncTexture[10]
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INSERT_PADDING_BYTES(1); // OmapReserved
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} vtg;
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struct {
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INSERT_PADDING_BYTES(3); // ImapSystemValuesA
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INSERT_PADDING_BYTES(1); // ImapSystemValuesB
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INSERT_PADDING_BYTES(32); // ImapGenericVector[32]
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INSERT_PADDING_BYTES(2); // ImapColor
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INSERT_PADDING_BYTES(2); // ImapSystemValuesC
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INSERT_PADDING_BYTES(10); // ImapFixedFncTexture[10]
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INSERT_PADDING_BYTES(2); // ImapReserved
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struct {
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u32 target;
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union {
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BitField<0, 1, u32> sample_mask;
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BitField<1, 1, u32> depth;
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BitField<2, 30, u32> reserved;
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};
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} omap;
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bool IsColorComponentOutputEnabled(u32 render_target, u32 component) const {
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const u32 bit = render_target * 4 + component;
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return omap.target & (1 << bit);
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}
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} ps;
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};
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};
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static_assert(sizeof(Header) == 0x50, "Incorrect structure size");
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} // namespace Tegra::Shader
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@ -12,6 +12,7 @@
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/engines/shader_header.h"
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#include "video_core/renderer_opengl/gl_rasterizer.h"
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#include "video_core/renderer_opengl/gl_shader_decompiler.h"
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@ -26,7 +27,7 @@ using Tegra::Shader::Sampler;
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using Tegra::Shader::SubOp;
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constexpr u32 PROGRAM_END = MAX_PROGRAM_CODE_LENGTH;
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constexpr u32 PROGRAM_HEADER_SIZE = 0x50;
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constexpr u32 PROGRAM_HEADER_SIZE = sizeof(Tegra::Shader::Header);
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class DecompileFail : public std::runtime_error {
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public:
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@ -674,7 +675,7 @@ public:
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u32 main_offset, Maxwell3D::Regs::ShaderStage stage, const std::string& suffix)
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: subroutines(subroutines), program_code(program_code), main_offset(main_offset),
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stage(stage), suffix(suffix) {
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std::memcpy(&header, program_code.data(), sizeof(Tegra::Shader::Header));
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Generate(suffix);
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}
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@ -688,23 +689,6 @@ public:
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}
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private:
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// Shader program header for a Fragment Shader.
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struct FragmentHeader {
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INSERT_PADDING_WORDS(5);
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INSERT_PADDING_WORDS(13);
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u32 enabled_color_outputs;
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union {
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BitField<0, 1, u32> writes_samplemask;
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BitField<1, 1, u32> writes_depth;
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};
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bool IsColorComponentOutputEnabled(u32 render_target, u32 component) const {
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const u32 bit = render_target * 4 + component;
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return enabled_color_outputs & (1 << bit);
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}
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};
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static_assert(sizeof(FragmentHeader) == PROGRAM_HEADER_SIZE, "FragmentHeader size is wrong");
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/// Gets the Subroutine object corresponding to the specified address.
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const Subroutine& GetSubroutine(u32 begin, u32 end) const {
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const auto iter = subroutines.find(Subroutine{begin, end, suffix});
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@ -1010,10 +994,8 @@ private:
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/// Writes the output values from a fragment shader to the corresponding GLSL output variables.
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void EmitFragmentOutputsWrite() {
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ASSERT(stage == Maxwell3D::Regs::ShaderStage::Fragment);
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FragmentHeader header;
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std::memcpy(&header, program_code.data(), PROGRAM_HEADER_SIZE);
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ASSERT_MSG(header.writes_samplemask == 0, "Samplemask write is unimplemented");
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ASSERT_MSG(header.ps.omap.sample_mask == 0, "Samplemask write is unimplemented");
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// Write the color outputs using the data in the shader registers, disabled
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// rendertargets/components are skipped in the register assignment.
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@ -1022,7 +1004,7 @@ private:
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++render_target) {
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// TODO(Subv): Figure out how dual-source blending is configured in the Switch.
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for (u32 component = 0; component < 4; ++component) {
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if (header.IsColorComponentOutputEnabled(render_target, component)) {
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if (header.ps.IsColorComponentOutputEnabled(render_target, component)) {
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shader.AddLine(fmt::format("FragColor{}[{}] = {};", render_target, component,
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regs.GetRegisterAsFloat(current_reg)));
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++current_reg;
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@ -1030,7 +1012,7 @@ private:
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}
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}
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if (header.writes_depth) {
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if (header.ps.omap.depth) {
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// The depth output is always 2 registers after the last color output, and current_reg
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// already contains one past the last color register.
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@ -2666,6 +2648,7 @@ private:
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private:
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const std::set<Subroutine>& subroutines;
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const ProgramCode& program_code;
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Tegra::Shader::Header header;
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const u32 main_offset;
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Maxwell3D::Regs::ShaderStage stage;
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const std::string& suffix;
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