video_core: Move command buffer loop.
This moves the hot loop into video_core. This refactoring shall reduce the CPU overhead of calling ProcessCommandList.
This commit is contained in:
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c560043581
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0cfb0bacb2
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@ -8,6 +8,7 @@
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#include "core/core.h"
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#include "core/hle/service/nvdrv/devices/nvhost_gpu.h"
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#include "core/memory.h"
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#include "video_core/command_processor.h"
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#include "video_core/gpu.h"
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#include "video_core/memory_manager.h"
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@ -134,17 +135,16 @@ u32 nvhost_gpu::SubmitGPFIFO(const std::vector<u8>& input, std::vector<u8>& outp
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LOG_WARNING(Service_NVDRV, "(STUBBED) called, gpfifo={:X}, num_entries={:X}, flags={:X}",
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params.address, params.num_entries, params.flags);
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ASSERT_MSG(input.size() ==
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sizeof(IoctlSubmitGpfifo) + params.num_entries * sizeof(IoctlGpfifoEntry),
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ASSERT_MSG(input.size() == sizeof(IoctlSubmitGpfifo) +
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params.num_entries * sizeof(Tegra::CommandListHeader),
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"Incorrect input size");
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std::vector<IoctlGpfifoEntry> entries(params.num_entries);
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std::vector<Tegra::CommandListHeader> entries(params.num_entries);
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std::memcpy(entries.data(), &input[sizeof(IoctlSubmitGpfifo)],
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params.num_entries * sizeof(IoctlGpfifoEntry));
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for (auto entry : entries) {
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Tegra::GPUVAddr va_addr = entry.Address();
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Core::System::GetInstance().GPU().ProcessCommandList(va_addr, entry.sz);
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}
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params.num_entries * sizeof(Tegra::CommandListHeader));
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Core::System::GetInstance().GPU().ProcessCommandLists(entries);
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params.fence_out.id = 0;
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params.fence_out.value = 0;
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std::memcpy(output.data(), ¶ms, sizeof(IoctlSubmitGpfifo));
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@ -160,14 +160,12 @@ u32 nvhost_gpu::KickoffPB(const std::vector<u8>& input, std::vector<u8>& output)
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LOG_WARNING(Service_NVDRV, "(STUBBED) called, gpfifo={:X}, num_entries={:X}, flags={:X}",
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params.address, params.num_entries, params.flags);
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std::vector<IoctlGpfifoEntry> entries(params.num_entries);
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std::vector<Tegra::CommandListHeader> entries(params.num_entries);
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Memory::ReadBlock(params.address, entries.data(),
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params.num_entries * sizeof(IoctlGpfifoEntry));
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params.num_entries * sizeof(Tegra::CommandListHeader));
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Core::System::GetInstance().GPU().ProcessCommandLists(entries);
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for (auto entry : entries) {
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Tegra::GPUVAddr va_addr = entry.Address();
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Core::System::GetInstance().GPU().ProcessCommandList(va_addr, entry.sz);
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}
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params.fence_out.id = 0;
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params.fence_out.value = 0;
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std::memcpy(output.data(), ¶ms, output.size());
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@ -10,7 +10,6 @@
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#include "common/common_types.h"
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#include "common/swap.h"
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#include "core/hle/service/nvdrv/devices/nvdevice.h"
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#include "video_core/memory_manager.h"
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namespace Service::Nvidia::Devices {
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@ -151,22 +150,6 @@ private:
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};
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static_assert(sizeof(IoctlAllocObjCtx) == 16, "IoctlAllocObjCtx is incorrect size");
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struct IoctlGpfifoEntry {
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u32_le entry0; // gpu_va_lo
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union {
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u32_le entry1; // gpu_va_hi | (unk_0x02 << 0x08) | (size << 0x0A) | (unk_0x01 << 0x1F)
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BitField<0, 8, u32_le> gpu_va_hi;
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BitField<8, 2, u32_le> unk1;
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BitField<10, 21, u32_le> sz;
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BitField<31, 1, u32_le> unk2;
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};
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Tegra::GPUVAddr Address() const {
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return (static_cast<Tegra::GPUVAddr>(gpu_va_hi) << 32) | entry0;
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}
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};
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static_assert(sizeof(IoctlGpfifoEntry) == 8, "IoctlGpfifoEntry is incorrect size");
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struct IoctlSubmitGpfifo {
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u64_le address; // pointer to gpfifo entry structs
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u32_le num_entries; // number of fence objects being submitted
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@ -69,57 +69,64 @@ void GPU::WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params)
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}
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}
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void GPU::ProcessCommandList(GPUVAddr address, u32 size) {
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const boost::optional<VAddr> head_address = memory_manager->GpuToCpuAddress(address);
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VAddr current_addr = *head_address;
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while (current_addr < *head_address + size * sizeof(CommandHeader)) {
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const CommandHeader header = {Memory::Read32(current_addr)};
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current_addr += sizeof(u32);
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MICROPROFILE_DEFINE(ProcessCommandLists, "GPU", "Execute command buffer", MP_RGB(128, 128, 192));
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switch (header.mode.Value()) {
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case SubmissionMode::IncreasingOld:
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case SubmissionMode::Increasing: {
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// Increase the method value with each argument.
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for (unsigned i = 0; i < header.arg_count; ++i) {
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WriteReg(header.method + i, header.subchannel, Memory::Read32(current_addr),
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header.arg_count - i - 1);
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current_addr += sizeof(u32);
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}
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break;
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}
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case SubmissionMode::NonIncreasingOld:
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case SubmissionMode::NonIncreasing: {
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// Use the same method value for all arguments.
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for (unsigned i = 0; i < header.arg_count; ++i) {
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WriteReg(header.method, header.subchannel, Memory::Read32(current_addr),
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header.arg_count - i - 1);
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current_addr += sizeof(u32);
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}
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break;
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}
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case SubmissionMode::IncreaseOnce: {
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ASSERT(header.arg_count.Value() >= 1);
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// Use the original method for the first argument and then the next method for all other
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// arguments.
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WriteReg(header.method, header.subchannel, Memory::Read32(current_addr),
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header.arg_count - 1);
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void GPU::ProcessCommandLists(const std::vector<CommandListHeader>& commands) {
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MICROPROFILE_SCOPE(ProcessCommandLists);
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for (auto entry : commands) {
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Tegra::GPUVAddr address = entry.Address();
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u32 size = entry.sz;
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const boost::optional<VAddr> head_address = memory_manager->GpuToCpuAddress(address);
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VAddr current_addr = *head_address;
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while (current_addr < *head_address + size * sizeof(CommandHeader)) {
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const CommandHeader header = {Memory::Read32(current_addr)};
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current_addr += sizeof(u32);
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for (unsigned i = 1; i < header.arg_count; ++i) {
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WriteReg(header.method + 1, header.subchannel, Memory::Read32(current_addr),
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header.arg_count - i - 1);
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current_addr += sizeof(u32);
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switch (header.mode.Value()) {
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case SubmissionMode::IncreasingOld:
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case SubmissionMode::Increasing: {
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// Increase the method value with each argument.
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for (unsigned i = 0; i < header.arg_count; ++i) {
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WriteReg(header.method + i, header.subchannel, Memory::Read32(current_addr),
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header.arg_count - i - 1);
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current_addr += sizeof(u32);
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}
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break;
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}
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case SubmissionMode::NonIncreasingOld:
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case SubmissionMode::NonIncreasing: {
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// Use the same method value for all arguments.
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for (unsigned i = 0; i < header.arg_count; ++i) {
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WriteReg(header.method, header.subchannel, Memory::Read32(current_addr),
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header.arg_count - i - 1);
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current_addr += sizeof(u32);
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}
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break;
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}
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case SubmissionMode::IncreaseOnce: {
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ASSERT(header.arg_count.Value() >= 1);
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// Use the original method for the first argument and then the next method for all
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// other arguments.
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WriteReg(header.method, header.subchannel, Memory::Read32(current_addr),
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header.arg_count - 1);
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current_addr += sizeof(u32);
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for (unsigned i = 1; i < header.arg_count; ++i) {
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WriteReg(header.method + 1, header.subchannel, Memory::Read32(current_addr),
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header.arg_count - i - 1);
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current_addr += sizeof(u32);
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}
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break;
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}
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case SubmissionMode::Inline: {
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// The register value is stored in the bits 16-28 as an immediate
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WriteReg(header.method, header.subchannel, header.inline_data, 0);
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break;
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}
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default:
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UNIMPLEMENTED();
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}
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break;
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}
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case SubmissionMode::Inline: {
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// The register value is stored in the bits 16-28 as an immediate
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WriteReg(header.method, header.subchannel, header.inline_data, 0);
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break;
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}
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default:
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UNIMPLEMENTED();
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}
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}
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}
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@ -7,6 +7,7 @@
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#include <type_traits>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "video_core/memory_manager.h"
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namespace Tegra {
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@ -19,6 +20,22 @@ enum class SubmissionMode : u32 {
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IncreaseOnce = 5
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};
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struct CommandListHeader {
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u32 entry0; // gpu_va_lo
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union {
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u32 entry1; // gpu_va_hi | (unk_0x02 << 0x08) | (size << 0x0A) | (unk_0x01 << 0x1F)
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BitField<0, 8, u32> gpu_va_hi;
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BitField<8, 2, u32> unk1;
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BitField<10, 21, u32> sz;
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BitField<31, 1, u32> unk2;
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};
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GPUVAddr Address() const {
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return (static_cast<GPUVAddr>(gpu_va_hi) << 32) | entry0;
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}
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};
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static_assert(sizeof(CommandListHeader) == 8, "CommandListHeader is incorrect size");
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union CommandHeader {
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u32 hex;
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@ -6,6 +6,7 @@
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#include <array>
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#include <memory>
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#include <vector>
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#include "common/common_types.h"
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#include "core/hle/service/nvflinger/buffer_queue.h"
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#include "video_core/memory_manager.h"
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@ -67,6 +68,7 @@ u32 RenderTargetBytesPerPixel(RenderTargetFormat format);
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/// Returns the number of bytes per pixel of each depth format.
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u32 DepthFormatBytesPerPixel(DepthFormat format);
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struct CommandListHeader;
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class DebugContext;
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/**
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~GPU();
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/// Processes a command list stored at the specified address in GPU memory.
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void ProcessCommandList(GPUVAddr address, u32 size);
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void ProcessCommandLists(const std::vector<CommandListHeader>& commands);
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/// Returns a reference to the Maxwell3D GPU engine.
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Engines::Maxwell3D& Maxwell3D();
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